227 lines
5.8 KiB
C
227 lines
5.8 KiB
C
/*
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* Platform setup for the Freescale mpc885ads board
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*
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* Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* Copyright 2005 MontaVista Software Inc.
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*
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* Heavily modified by Scott Wood <scottwood@freescale.com>
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* Copyright 2007 Freescale Semiconductor, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/param.h>
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#include <linux/string.h>
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#include <linux/ioport.h>
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#include <linux/device.h>
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#include <linux/delay.h>
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#include <linux/fs_enet_pd.h>
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#include <linux/fs_uart_pd.h>
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#include <linux/fsl_devices.h>
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#include <linux/mii.h>
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#include <linux/of_address.h>
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#include <linux/of_fdt.h>
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#include <linux/of_platform.h>
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#include <asm/delay.h>
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#include <asm/io.h>
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#include <asm/machdep.h>
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#include <asm/page.h>
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#include <asm/processor.h>
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#include <asm/time.h>
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#include <asm/8xx_immap.h>
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#include <asm/cpm1.h>
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#include <asm/fs_pd.h>
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#include <asm/udbg.h>
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#include "mpc885ads.h"
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#include "mpc8xx.h"
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static u32 __iomem *bcsr, *bcsr5;
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struct cpm_pin {
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int port, pin, flags;
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};
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static struct cpm_pin mpc885ads_pins[] = {
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/* SMC1 */
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{CPM_PORTB, 24, CPM_PIN_INPUT}, /* RX */
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{CPM_PORTB, 25, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
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/* SMC2 */
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#ifndef CONFIG_MPC8xx_SECOND_ETH_FEC2
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{CPM_PORTE, 21, CPM_PIN_INPUT}, /* RX */
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{CPM_PORTE, 20, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TX */
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#endif
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/* SCC3 */
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{CPM_PORTA, 9, CPM_PIN_INPUT}, /* RX */
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{CPM_PORTA, 8, CPM_PIN_INPUT}, /* TX */
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{CPM_PORTC, 4, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* RENA */
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{CPM_PORTC, 5, CPM_PIN_INPUT | CPM_PIN_SECONDARY | CPM_PIN_GPIO}, /* CLSN */
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{CPM_PORTE, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY}, /* TENA */
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{CPM_PORTE, 17, CPM_PIN_INPUT}, /* CLK5 */
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{CPM_PORTE, 16, CPM_PIN_INPUT}, /* CLK6 */
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/* MII1 */
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{CPM_PORTA, 0, CPM_PIN_INPUT},
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{CPM_PORTA, 1, CPM_PIN_INPUT},
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{CPM_PORTA, 2, CPM_PIN_INPUT},
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{CPM_PORTA, 3, CPM_PIN_INPUT},
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{CPM_PORTA, 4, CPM_PIN_OUTPUT},
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{CPM_PORTA, 10, CPM_PIN_OUTPUT},
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{CPM_PORTA, 11, CPM_PIN_OUTPUT},
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{CPM_PORTB, 19, CPM_PIN_INPUT},
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{CPM_PORTB, 31, CPM_PIN_INPUT},
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{CPM_PORTC, 12, CPM_PIN_INPUT},
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{CPM_PORTC, 13, CPM_PIN_INPUT},
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{CPM_PORTE, 30, CPM_PIN_OUTPUT},
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{CPM_PORTE, 31, CPM_PIN_OUTPUT},
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/* MII2 */
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#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
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{CPM_PORTE, 14, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{CPM_PORTE, 15, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{CPM_PORTE, 16, CPM_PIN_OUTPUT},
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{CPM_PORTE, 17, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{CPM_PORTE, 18, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{CPM_PORTE, 19, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{CPM_PORTE, 20, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{CPM_PORTE, 21, CPM_PIN_OUTPUT},
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{CPM_PORTE, 22, CPM_PIN_OUTPUT},
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{CPM_PORTE, 23, CPM_PIN_OUTPUT},
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{CPM_PORTE, 24, CPM_PIN_OUTPUT},
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{CPM_PORTE, 25, CPM_PIN_OUTPUT},
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{CPM_PORTE, 26, CPM_PIN_OUTPUT},
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{CPM_PORTE, 27, CPM_PIN_OUTPUT},
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{CPM_PORTE, 28, CPM_PIN_OUTPUT},
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{CPM_PORTE, 29, CPM_PIN_OUTPUT},
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#endif
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/* I2C */
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{CPM_PORTB, 26, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
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{CPM_PORTB, 27, CPM_PIN_INPUT | CPM_PIN_OPENDRAIN},
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};
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static void __init init_ioports(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(mpc885ads_pins); i++) {
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struct cpm_pin *pin = &mpc885ads_pins[i];
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cpm1_set_pin(pin->port, pin->pin, pin->flags);
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}
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cpm1_clk_setup(CPM_CLK_SMC1, CPM_BRG1, CPM_CLK_RTX);
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cpm1_clk_setup(CPM_CLK_SMC2, CPM_BRG2, CPM_CLK_RTX);
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cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK5, CPM_CLK_TX);
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cpm1_clk_setup(CPM_CLK_SCC3, CPM_CLK6, CPM_CLK_RX);
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/* Set FEC1 and FEC2 to MII mode */
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clrbits32(&mpc8xx_immr->im_cpm.cp_cptr, 0x00000180);
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}
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static void __init mpc885ads_setup_arch(void)
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{
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struct device_node *np;
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cpm_reset();
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init_ioports();
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np = of_find_compatible_node(NULL, NULL, "fsl,mpc885ads-bcsr");
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if (!np) {
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printk(KERN_CRIT "Could not find fsl,mpc885ads-bcsr node\n");
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return;
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}
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bcsr = of_iomap(np, 0);
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bcsr5 = of_iomap(np, 1);
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of_node_put(np);
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if (!bcsr || !bcsr5) {
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printk(KERN_CRIT "Could not remap BCSR\n");
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return;
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}
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clrbits32(&bcsr[1], BCSR1_RS232EN_1);
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#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
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setbits32(&bcsr[1], BCSR1_RS232EN_2);
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#else
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clrbits32(&bcsr[1], BCSR1_RS232EN_2);
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#endif
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clrbits32(bcsr5, BCSR5_MII1_EN);
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setbits32(bcsr5, BCSR5_MII1_RST);
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udelay(1000);
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clrbits32(bcsr5, BCSR5_MII1_RST);
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#ifdef CONFIG_MPC8xx_SECOND_ETH_FEC2
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clrbits32(bcsr5, BCSR5_MII2_EN);
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setbits32(bcsr5, BCSR5_MII2_RST);
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udelay(1000);
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clrbits32(bcsr5, BCSR5_MII2_RST);
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#else
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setbits32(bcsr5, BCSR5_MII2_EN);
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#endif
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#ifdef CONFIG_MPC8xx_SECOND_ETH_SCC3
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clrbits32(&bcsr[4], BCSR4_ETH10_RST);
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udelay(1000);
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setbits32(&bcsr[4], BCSR4_ETH10_RST);
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setbits32(&bcsr[1], BCSR1_ETHEN);
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np = of_find_node_by_path("/soc@ff000000/cpm@9c0/serial@a80");
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#else
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np = of_find_node_by_path("/soc@ff000000/cpm@9c0/ethernet@a40");
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#endif
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/* The SCC3 enet registers overlap the SMC1 registers, so
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* one of the two must be removed from the device tree.
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*/
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if (np) {
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of_detach_node(np);
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of_node_put(np);
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}
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}
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static int __init mpc885ads_probe(void)
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{
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return of_machine_is_compatible("fsl,mpc885ads");
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}
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static const struct of_device_id of_bus_ids[] __initconst = {
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{ .name = "soc", },
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{ .name = "cpm", },
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{ .name = "localbus", },
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{},
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};
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static int __init declare_of_platform_devices(void)
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{
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/* Publish the QE devices */
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of_platform_bus_probe(NULL, of_bus_ids, NULL);
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return 0;
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}
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machine_device_initcall(mpc885_ads, declare_of_platform_devices);
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define_machine(mpc885_ads) {
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.name = "Freescale MPC885 ADS",
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.probe = mpc885ads_probe,
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.setup_arch = mpc885ads_setup_arch,
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.init_IRQ = mpc8xx_pics_init,
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.get_irq = mpc8xx_get_irq,
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.restart = mpc8xx_restart,
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.calibrate_decr = mpc8xx_calibrate_decr,
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.set_rtc_time = mpc8xx_set_rtc_time,
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.get_rtc_time = mpc8xx_get_rtc_time,
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.progress = udbg_progress,
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};
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