106 lines
3.3 KiB
C
106 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_CPUIDLE_H
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#define _ASM_POWERPC_CPUIDLE_H
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#ifdef CONFIG_PPC_POWERNV
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/* Thread state used in powernv idle state management */
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#define PNV_THREAD_RUNNING 0
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#define PNV_THREAD_NAP 1
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#define PNV_THREAD_SLEEP 2
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#define PNV_THREAD_WINKLE 3
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/*
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* Core state used in powernv idle for POWER8.
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*
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* The lock bit synchronizes updates to the state, as well as parts of the
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* sleep/wake code (see kernel/idle_book3s.S).
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*
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* Bottom 8 bits track the idle state of each thread. Bit is cleared before
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* the thread executes an idle instruction (nap/sleep/winkle).
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*
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* Then there is winkle tracking. A core does not lose complete state
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* until every thread is in winkle. So the winkle count field counts the
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* number of threads in winkle (small window of false positives is okay
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* around the sleep/wake, so long as there are no false negatives).
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*
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* When the winkle count reaches 8 (the COUNT_ALL_BIT becomes set), then
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* the THREAD_WINKLE_BITS are set, which indicate which threads have not
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* yet woken from the winkle state.
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*/
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#define PNV_CORE_IDLE_LOCK_BIT 0x10000000
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#define PNV_CORE_IDLE_WINKLE_COUNT 0x00010000
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#define PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT 0x00080000
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#define PNV_CORE_IDLE_WINKLE_COUNT_BITS 0x000F0000
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#define PNV_CORE_IDLE_THREAD_WINKLE_BITS_SHIFT 8
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#define PNV_CORE_IDLE_THREAD_WINKLE_BITS 0x0000FF00
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#define PNV_CORE_IDLE_THREAD_BITS 0x000000FF
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/*
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* ============================ NOTE =================================
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* The older firmware populates only the RL field in the psscr_val and
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* sets the psscr_mask to 0xf. On such a firmware, the kernel sets the
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* remaining PSSCR fields to default values as follows:
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*
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* - ESL and EC bits are to 1. So wakeup from any stop state will be
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* at vector 0x100.
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*
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* - MTL and PSLL are set to the maximum allowed value as per the ISA,
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* i.e. 15.
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*
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* - The Transition Rate, TR is set to the Maximum value 3.
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*/
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#define PSSCR_HV_DEFAULT_VAL (PSSCR_ESL | PSSCR_EC | \
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PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
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PSSCR_MTL_MASK)
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#define PSSCR_HV_DEFAULT_MASK (PSSCR_ESL | PSSCR_EC | \
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PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
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PSSCR_MTL_MASK | PSSCR_RL_MASK)
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#define PSSCR_EC_SHIFT 20
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#define PSSCR_ESL_SHIFT 21
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#define GET_PSSCR_EC(x) (((x) & PSSCR_EC) >> PSSCR_EC_SHIFT)
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#define GET_PSSCR_ESL(x) (((x) & PSSCR_ESL) >> PSSCR_ESL_SHIFT)
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#define GET_PSSCR_RL(x) ((x) & PSSCR_RL_MASK)
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#define ERR_EC_ESL_MISMATCH -1
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#define ERR_DEEP_STATE_ESL_MISMATCH -2
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#ifndef __ASSEMBLY__
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/* Additional SPRs that need to be saved/restored during stop */
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struct stop_sprs {
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u64 pid;
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u64 ldbar;
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u64 fscr;
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u64 hfscr;
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u64 mmcr1;
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u64 mmcr2;
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u64 mmcra;
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};
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extern u32 pnv_fastsleep_workaround_at_entry[];
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extern u32 pnv_fastsleep_workaround_at_exit[];
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extern u64 pnv_first_deep_stop_state;
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unsigned long pnv_cpu_offline(unsigned int cpu);
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int validate_psscr_val_mask(u64 *psscr_val, u64 *psscr_mask, u32 flags);
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static inline void report_invalid_psscr_val(u64 psscr_val, int err)
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{
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switch (err) {
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case ERR_EC_ESL_MISMATCH:
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pr_warn("Invalid psscr 0x%016llx : ESL,EC bits unequal",
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psscr_val);
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break;
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case ERR_DEEP_STATE_ESL_MISMATCH:
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pr_warn("Invalid psscr 0x%016llx : ESL cleared for deep stop-state",
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psscr_val);
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}
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}
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#endif
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#endif
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#endif
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