117 lines
5.4 KiB
C
117 lines
5.4 KiB
C
/* mach/dma.h - arch-specific DMA defines
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*
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* Copyright 2011 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef _MACH_DMA_H_
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#define _MACH_DMA_H_
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#define CH_SPORT0_TX 0
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#define CH_SPORT0_RX 1
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#define CH_SPORT1_TX 2
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#define CH_SPORT1_RX 3
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#define CH_SPORT2_TX 4
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#define CH_SPORT2_RX 5
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#define CH_SPI0_TX 6
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#define CH_SPI0_RX 7
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#define CH_SPI1_TX 8
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#define CH_SPI1_RX 9
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#define CH_RSI 10
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#define CH_SDU 11
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#define CH_LP0 13
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#define CH_LP1 14
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#define CH_LP2 15
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#define CH_LP3 16
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#define CH_UART0_TX 17
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#define CH_UART0_RX 18
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#define CH_UART1_TX 19
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#define CH_UART1_RX 20
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#define CH_MEM_STREAM0_SRC_CRC0 21
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#define CH_MEM_STREAM0_SRC CH_MEM_STREAM0_SRC_CRC0
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#define CH_MEM_STREAM0_DEST_CRC0 22
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#define CH_MEM_STREAM0_DEST CH_MEM_STREAM0_DEST_CRC0
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#define CH_MEM_STREAM1_SRC_CRC1 23
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#define CH_MEM_STREAM1_SRC CH_MEM_STREAM1_SRC_CRC1
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#define CH_MEM_STREAM1_DEST_CRC1 24
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#define CH_MEM_STREAM1_DEST CH_MEM_STREAM1_DEST_CRC1
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#define CH_MEM_STREAM2_SRC 25
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#define CH_MEM_STREAM2_DEST 26
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#define CH_MEM_STREAM3_SRC 27
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#define CH_MEM_STREAM3_DEST 28
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#define CH_EPPI0_CH0 29
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#define CH_EPPI0_CH1 30
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#define CH_EPPI1_CH0 31
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#define CH_EPPI1_CH1 32
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#define CH_EPPI2_CH0 33
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#define CH_EPPI2_CH1 34
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#define CH_PIXC_CH0 35
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#define CH_PIXC_CH1 36
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#define CH_PIXC_CH2 37
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#define CH_PVP_CPDOB 38
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#define CH_PVP_CPDOC 39
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#define CH_PVP_CPSTAT 40
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#define CH_PVP_CPCI 41
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#define CH_PVP_MPDO 42
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#define CH_PVP_MPDI 43
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#define CH_PVP_MPSTAT 44
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#define CH_PVP_MPCI 45
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#define CH_PVP_CPDOA 46
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#define MAX_DMA_CHANNELS 47
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#define MAX_DMA_SUSPEND_CHANNELS 0
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#define DMA_MMR_SIZE_32
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#define bfin_read_MDMA_S0_CONFIG bfin_read_MDMA0_SRC_CRC0_CONFIG
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#define bfin_write_MDMA_S0_CONFIG bfin_write_MDMA0_SRC_CRC0_CONFIG
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#define bfin_read_MDMA_S0_IRQ_STATUS bfin_read_MDMA0_SRC_CRC0_IRQ_STATUS
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#define bfin_write_MDMA_S0_IRQ_STATUS bfin_write_MDMA0_SRC_CRC0_IRQ_STATUS
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#define bfin_write_MDMA_S0_START_ADDR bfin_write_MDMA0_SRC_CRC0_START_ADDR
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#define bfin_write_MDMA_S0_X_COUNT bfin_write_MDMA0_SRC_CRC0_X_COUNT
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#define bfin_write_MDMA_S0_X_MODIFY bfin_write_MDMA0_SRC_CRC0_X_MODIFY
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#define bfin_write_MDMA_S0_Y_COUNT bfin_write_MDMA0_SRC_CRC0_Y_COUNT
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#define bfin_write_MDMA_S0_Y_MODIFY bfin_write_MDMA0_SRC_CRC0_Y_MODIFY
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#define bfin_read_MDMA_D0_CONFIG bfin_read_MDMA0_DEST_CRC0_CONFIG
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#define bfin_write_MDMA_D0_CONFIG bfin_write_MDMA0_DEST_CRC0_CONFIG
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#define bfin_read_MDMA_D0_IRQ_STATUS bfin_read_MDMA0_DEST_CRC0_IRQ_STATUS
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#define bfin_write_MDMA_D0_IRQ_STATUS bfin_write_MDMA0_DEST_CRC0_IRQ_STATUS
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#define bfin_write_MDMA_D0_START_ADDR bfin_write_MDMA0_DEST_CRC0_START_ADDR
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#define bfin_write_MDMA_D0_X_COUNT bfin_write_MDMA0_DEST_CRC0_X_COUNT
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#define bfin_write_MDMA_D0_X_MODIFY bfin_write_MDMA0_DEST_CRC0_X_MODIFY
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#define bfin_write_MDMA_D0_Y_COUNT bfin_write_MDMA0_DEST_CRC0_Y_COUNT
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#define bfin_write_MDMA_D0_Y_MODIFY bfin_write_MDMA0_DEST_CRC0_Y_MODIFY
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#define bfin_read_MDMA_S1_CONFIG bfin_read_MDMA1_SRC_CRC1_CONFIG
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#define bfin_write_MDMA_S1_CONFIG bfin_write_MDMA1_SRC_CRC1_CONFIG
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#define bfin_read_MDMA_D1_CONFIG bfin_read_MDMA1_DEST_CRC1_CONFIG
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#define bfin_write_MDMA_D1_CONFIG bfin_write_MDMA1_DEST_CRC1_CONFIG
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#define bfin_read_MDMA_D1_IRQ_STATUS bfin_read_MDMA1_DEST_CRC1_IRQ_STATUS
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#define bfin_write_MDMA_D1_IRQ_STATUS bfin_write_MDMA1_DEST_CRC1_IRQ_STATUS
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#define bfin_read_MDMA_S3_CONFIG bfin_read_MDMA3_SRC_CONFIG
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#define bfin_write_MDMA_S3_CONFIG bfin_write_MDMA3_SRC_CONFIG
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#define bfin_read_MDMA_S3_IRQ_STATUS bfin_read_MDMA3_SRC_IRQ_STATUS
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#define bfin_write_MDMA_S3_IRQ_STATUS bfin_write_MDMA3_SRC_IRQ_STATUS
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#define bfin_write_MDMA_S3_START_ADDR bfin_write_MDMA3_SRC_START_ADDR
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#define bfin_write_MDMA_S3_X_COUNT bfin_write_MDMA3_SRC_X_COUNT
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#define bfin_write_MDMA_S3_X_MODIFY bfin_write_MDMA3_SRC_X_MODIFY
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#define bfin_write_MDMA_S3_Y_COUNT bfin_write_MDMA3_SRC_Y_COUNT
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#define bfin_write_MDMA_S3_Y_MODIFY bfin_write_MDMA3_SRC_Y_MODIFY
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#define bfin_read_MDMA_D3_CONFIG bfin_read_MDMA3_DEST_CONFIG
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#define bfin_write_MDMA_D3_CONFIG bfin_write_MDMA3_DEST_CONFIG
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#define bfin_read_MDMA_D3_IRQ_STATUS bfin_read_MDMA3_DEST_IRQ_STATUS
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#define bfin_write_MDMA_D3_IRQ_STATUS bfin_write_MDMA3_DEST_IRQ_STATUS
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#define bfin_write_MDMA_D3_START_ADDR bfin_write_MDMA3_DEST_START_ADDR
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#define bfin_write_MDMA_D3_X_COUNT bfin_write_MDMA3_DEST_X_COUNT
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#define bfin_write_MDMA_D3_X_MODIFY bfin_write_MDMA3_DEST_X_MODIFY
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#define bfin_write_MDMA_D3_Y_COUNT bfin_write_MDMA3_DEST_Y_COUNT
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#define bfin_write_MDMA_D3_Y_MODIFY bfin_write_MDMA3_DEST_Y_MODIFY
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#define MDMA_S0_NEXT_DESC_PTR MDMA0_SRC_CRC0_NEXT_DESC_PTR
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#define MDMA_D0_NEXT_DESC_PTR MDMA0_DEST_CRC0_NEXT_DESC_PTR
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#define MDMA_S1_NEXT_DESC_PTR MDMA1_SRC_CRC1_NEXT_DESC_PTR
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#define MDMA_D1_NEXT_DESC_PTR MDMA1_DEST_CRC1_NEXT_DESC_PTR
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#endif
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