474 lines
12 KiB
C
474 lines
12 KiB
C
/*
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* arch/blackfin/kernel/kgdb.c - Blackfin kgdb pieces
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*
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* Copyright 2005-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/ptrace.h> /* for linux pt_regs struct */
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#include <linux/kgdb.h>
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#include <linux/uaccess.h>
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#include <asm/irq_regs.h>
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void pt_regs_to_gdb_regs(unsigned long *gdb_regs, struct pt_regs *regs)
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{
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gdb_regs[BFIN_R0] = regs->r0;
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gdb_regs[BFIN_R1] = regs->r1;
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gdb_regs[BFIN_R2] = regs->r2;
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gdb_regs[BFIN_R3] = regs->r3;
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gdb_regs[BFIN_R4] = regs->r4;
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gdb_regs[BFIN_R5] = regs->r5;
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gdb_regs[BFIN_R6] = regs->r6;
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gdb_regs[BFIN_R7] = regs->r7;
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gdb_regs[BFIN_P0] = regs->p0;
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gdb_regs[BFIN_P1] = regs->p1;
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gdb_regs[BFIN_P2] = regs->p2;
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gdb_regs[BFIN_P3] = regs->p3;
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gdb_regs[BFIN_P4] = regs->p4;
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gdb_regs[BFIN_P5] = regs->p5;
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gdb_regs[BFIN_SP] = regs->reserved;
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gdb_regs[BFIN_FP] = regs->fp;
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gdb_regs[BFIN_I0] = regs->i0;
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gdb_regs[BFIN_I1] = regs->i1;
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gdb_regs[BFIN_I2] = regs->i2;
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gdb_regs[BFIN_I3] = regs->i3;
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gdb_regs[BFIN_M0] = regs->m0;
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gdb_regs[BFIN_M1] = regs->m1;
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gdb_regs[BFIN_M2] = regs->m2;
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gdb_regs[BFIN_M3] = regs->m3;
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gdb_regs[BFIN_B0] = regs->b0;
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gdb_regs[BFIN_B1] = regs->b1;
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gdb_regs[BFIN_B2] = regs->b2;
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gdb_regs[BFIN_B3] = regs->b3;
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gdb_regs[BFIN_L0] = regs->l0;
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gdb_regs[BFIN_L1] = regs->l1;
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gdb_regs[BFIN_L2] = regs->l2;
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gdb_regs[BFIN_L3] = regs->l3;
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gdb_regs[BFIN_A0_DOT_X] = regs->a0x;
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gdb_regs[BFIN_A0_DOT_W] = regs->a0w;
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gdb_regs[BFIN_A1_DOT_X] = regs->a1x;
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gdb_regs[BFIN_A1_DOT_W] = regs->a1w;
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gdb_regs[BFIN_ASTAT] = regs->astat;
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gdb_regs[BFIN_RETS] = regs->rets;
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gdb_regs[BFIN_LC0] = regs->lc0;
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gdb_regs[BFIN_LT0] = regs->lt0;
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gdb_regs[BFIN_LB0] = regs->lb0;
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gdb_regs[BFIN_LC1] = regs->lc1;
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gdb_regs[BFIN_LT1] = regs->lt1;
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gdb_regs[BFIN_LB1] = regs->lb1;
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gdb_regs[BFIN_CYCLES] = 0;
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gdb_regs[BFIN_CYCLES2] = 0;
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gdb_regs[BFIN_USP] = regs->usp;
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gdb_regs[BFIN_SEQSTAT] = regs->seqstat;
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gdb_regs[BFIN_SYSCFG] = regs->syscfg;
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gdb_regs[BFIN_RETI] = regs->pc;
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gdb_regs[BFIN_RETX] = regs->retx;
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gdb_regs[BFIN_RETN] = regs->retn;
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gdb_regs[BFIN_RETE] = regs->rete;
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gdb_regs[BFIN_PC] = regs->pc;
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gdb_regs[BFIN_CC] = (regs->astat >> 5) & 1;
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gdb_regs[BFIN_EXTRA1] = 0;
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gdb_regs[BFIN_EXTRA2] = 0;
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gdb_regs[BFIN_EXTRA3] = 0;
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gdb_regs[BFIN_IPEND] = regs->ipend;
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}
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/*
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* Extracts ebp, esp and eip values understandable by gdb from the values
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* saved by switch_to.
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* thread.esp points to ebp. flags and ebp are pushed in switch_to hence esp
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* prior to entering switch_to is 8 greater than the value that is saved.
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* If switch_to changes, change following code appropriately.
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*/
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void sleeping_thread_to_gdb_regs(unsigned long *gdb_regs, struct task_struct *p)
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{
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gdb_regs[BFIN_SP] = p->thread.ksp;
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gdb_regs[BFIN_PC] = p->thread.pc;
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gdb_regs[BFIN_SEQSTAT] = p->thread.seqstat;
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}
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void gdb_regs_to_pt_regs(unsigned long *gdb_regs, struct pt_regs *regs)
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{
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regs->r0 = gdb_regs[BFIN_R0];
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regs->r1 = gdb_regs[BFIN_R1];
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regs->r2 = gdb_regs[BFIN_R2];
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regs->r3 = gdb_regs[BFIN_R3];
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regs->r4 = gdb_regs[BFIN_R4];
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regs->r5 = gdb_regs[BFIN_R5];
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regs->r6 = gdb_regs[BFIN_R6];
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regs->r7 = gdb_regs[BFIN_R7];
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regs->p0 = gdb_regs[BFIN_P0];
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regs->p1 = gdb_regs[BFIN_P1];
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regs->p2 = gdb_regs[BFIN_P2];
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regs->p3 = gdb_regs[BFIN_P3];
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regs->p4 = gdb_regs[BFIN_P4];
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regs->p5 = gdb_regs[BFIN_P5];
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regs->fp = gdb_regs[BFIN_FP];
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regs->i0 = gdb_regs[BFIN_I0];
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regs->i1 = gdb_regs[BFIN_I1];
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regs->i2 = gdb_regs[BFIN_I2];
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regs->i3 = gdb_regs[BFIN_I3];
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regs->m0 = gdb_regs[BFIN_M0];
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regs->m1 = gdb_regs[BFIN_M1];
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regs->m2 = gdb_regs[BFIN_M2];
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regs->m3 = gdb_regs[BFIN_M3];
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regs->b0 = gdb_regs[BFIN_B0];
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regs->b1 = gdb_regs[BFIN_B1];
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regs->b2 = gdb_regs[BFIN_B2];
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regs->b3 = gdb_regs[BFIN_B3];
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regs->l0 = gdb_regs[BFIN_L0];
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regs->l1 = gdb_regs[BFIN_L1];
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regs->l2 = gdb_regs[BFIN_L2];
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regs->l3 = gdb_regs[BFIN_L3];
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regs->a0x = gdb_regs[BFIN_A0_DOT_X];
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regs->a0w = gdb_regs[BFIN_A0_DOT_W];
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regs->a1x = gdb_regs[BFIN_A1_DOT_X];
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regs->a1w = gdb_regs[BFIN_A1_DOT_W];
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regs->rets = gdb_regs[BFIN_RETS];
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regs->lc0 = gdb_regs[BFIN_LC0];
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regs->lt0 = gdb_regs[BFIN_LT0];
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regs->lb0 = gdb_regs[BFIN_LB0];
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regs->lc1 = gdb_regs[BFIN_LC1];
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regs->lt1 = gdb_regs[BFIN_LT1];
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regs->lb1 = gdb_regs[BFIN_LB1];
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regs->usp = gdb_regs[BFIN_USP];
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regs->syscfg = gdb_regs[BFIN_SYSCFG];
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regs->retx = gdb_regs[BFIN_RETX];
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regs->retn = gdb_regs[BFIN_RETN];
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regs->rete = gdb_regs[BFIN_RETE];
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regs->pc = gdb_regs[BFIN_PC];
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#if 0 /* can't change these */
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regs->astat = gdb_regs[BFIN_ASTAT];
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regs->seqstat = gdb_regs[BFIN_SEQSTAT];
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regs->ipend = gdb_regs[BFIN_IPEND];
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#endif
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}
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static struct hw_breakpoint {
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unsigned int occupied:1;
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unsigned int skip:1;
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unsigned int enabled:1;
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unsigned int type:1;
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unsigned int dataacc:2;
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unsigned short count;
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unsigned int addr;
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} breakinfo[HW_WATCHPOINT_NUM];
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static int bfin_set_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
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{
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int breakno;
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int bfin_type;
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int dataacc = 0;
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switch (type) {
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case BP_HARDWARE_BREAKPOINT:
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bfin_type = TYPE_INST_WATCHPOINT;
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break;
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case BP_WRITE_WATCHPOINT:
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dataacc = 1;
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bfin_type = TYPE_DATA_WATCHPOINT;
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break;
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case BP_READ_WATCHPOINT:
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dataacc = 2;
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bfin_type = TYPE_DATA_WATCHPOINT;
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break;
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case BP_ACCESS_WATCHPOINT:
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dataacc = 3;
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bfin_type = TYPE_DATA_WATCHPOINT;
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break;
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default:
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return -ENOSPC;
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}
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/* Because hardware data watchpoint impelemented in current
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* Blackfin can not trigger an exception event as the hardware
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* instrction watchpoint does, we ignaore all data watch point here.
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* They can be turned on easily after future blackfin design
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* supports this feature.
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*/
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for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
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if (bfin_type == breakinfo[breakno].type
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&& !breakinfo[breakno].occupied) {
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breakinfo[breakno].occupied = 1;
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breakinfo[breakno].skip = 0;
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breakinfo[breakno].enabled = 1;
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breakinfo[breakno].addr = addr;
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breakinfo[breakno].dataacc = dataacc;
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breakinfo[breakno].count = 0;
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return 0;
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}
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return -ENOSPC;
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}
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static int bfin_remove_hw_break(unsigned long addr, int len, enum kgdb_bptype type)
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{
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int breakno;
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int bfin_type;
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switch (type) {
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case BP_HARDWARE_BREAKPOINT:
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bfin_type = TYPE_INST_WATCHPOINT;
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break;
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case BP_WRITE_WATCHPOINT:
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case BP_READ_WATCHPOINT:
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case BP_ACCESS_WATCHPOINT:
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bfin_type = TYPE_DATA_WATCHPOINT;
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break;
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default:
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return 0;
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}
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for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
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if (bfin_type == breakinfo[breakno].type
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&& breakinfo[breakno].occupied
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&& breakinfo[breakno].addr == addr) {
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breakinfo[breakno].occupied = 0;
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breakinfo[breakno].enabled = 0;
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}
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return 0;
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}
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static void bfin_remove_all_hw_break(void)
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{
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int breakno;
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memset(breakinfo, 0, sizeof(struct hw_breakpoint)*HW_WATCHPOINT_NUM);
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for (breakno = 0; breakno < HW_INST_WATCHPOINT_NUM; breakno++)
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breakinfo[breakno].type = TYPE_INST_WATCHPOINT;
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for (; breakno < HW_WATCHPOINT_NUM; breakno++)
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breakinfo[breakno].type = TYPE_DATA_WATCHPOINT;
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}
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static void bfin_correct_hw_break(void)
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{
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int breakno;
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unsigned int wpiactl = 0;
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unsigned int wpdactl = 0;
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int enable_wp = 0;
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for (breakno = 0; breakno < HW_WATCHPOINT_NUM; breakno++)
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if (breakinfo[breakno].enabled) {
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enable_wp = 1;
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switch (breakno) {
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case 0:
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wpiactl |= WPIAEN0|WPICNTEN0;
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bfin_write_WPIA0(breakinfo[breakno].addr);
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bfin_write_WPIACNT0(breakinfo[breakno].count
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+ breakinfo->skip);
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break;
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case 1:
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wpiactl |= WPIAEN1|WPICNTEN1;
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bfin_write_WPIA1(breakinfo[breakno].addr);
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bfin_write_WPIACNT1(breakinfo[breakno].count
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+ breakinfo->skip);
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break;
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case 2:
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wpiactl |= WPIAEN2|WPICNTEN2;
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bfin_write_WPIA2(breakinfo[breakno].addr);
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bfin_write_WPIACNT2(breakinfo[breakno].count
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+ breakinfo->skip);
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break;
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case 3:
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wpiactl |= WPIAEN3|WPICNTEN3;
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bfin_write_WPIA3(breakinfo[breakno].addr);
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bfin_write_WPIACNT3(breakinfo[breakno].count
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+ breakinfo->skip);
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break;
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case 4:
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wpiactl |= WPIAEN4|WPICNTEN4;
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bfin_write_WPIA4(breakinfo[breakno].addr);
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bfin_write_WPIACNT4(breakinfo[breakno].count
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+ breakinfo->skip);
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break;
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case 5:
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wpiactl |= WPIAEN5|WPICNTEN5;
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bfin_write_WPIA5(breakinfo[breakno].addr);
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bfin_write_WPIACNT5(breakinfo[breakno].count
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+ breakinfo->skip);
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break;
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case 6:
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wpdactl |= WPDAEN0|WPDCNTEN0|WPDSRC0;
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wpdactl |= breakinfo[breakno].dataacc
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<< WPDACC0_OFFSET;
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bfin_write_WPDA0(breakinfo[breakno].addr);
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bfin_write_WPDACNT0(breakinfo[breakno].count
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+ breakinfo->skip);
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break;
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case 7:
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wpdactl |= WPDAEN1|WPDCNTEN1|WPDSRC1;
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wpdactl |= breakinfo[breakno].dataacc
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<< WPDACC1_OFFSET;
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bfin_write_WPDA1(breakinfo[breakno].addr);
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bfin_write_WPDACNT1(breakinfo[breakno].count
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+ breakinfo->skip);
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break;
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}
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}
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/* Should enable WPPWR bit first before set any other
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* WPIACTL and WPDACTL bits */
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if (enable_wp) {
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bfin_write_WPIACTL(WPPWR);
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CSYNC();
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bfin_write_WPIACTL(wpiactl|WPPWR);
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bfin_write_WPDACTL(wpdactl);
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CSYNC();
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}
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}
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static void bfin_disable_hw_debug(struct pt_regs *regs)
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{
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/* Disable hardware debugging while we are in kgdb */
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bfin_write_WPIACTL(0);
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bfin_write_WPDACTL(0);
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CSYNC();
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}
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#ifdef CONFIG_SMP
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void kgdb_passive_cpu_callback(void *info)
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{
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kgdb_nmicallback(raw_smp_processor_id(), get_irq_regs());
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}
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void kgdb_roundup_cpus(unsigned long flags)
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{
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unsigned int cpu;
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for (cpu = cpumask_first(cpu_online_mask); cpu < nr_cpu_ids;
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cpu = cpumask_next(cpu, cpu_online_mask))
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smp_call_function_single(cpu, kgdb_passive_cpu_callback,
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NULL, 0);
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}
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void kgdb_roundup_cpu(int cpu, unsigned long flags)
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{
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smp_call_function_single(cpu, kgdb_passive_cpu_callback, NULL, 0);
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}
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#endif
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#ifdef CONFIG_IPIPE
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static unsigned long kgdb_arch_imask;
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#endif
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int kgdb_arch_handle_exception(int vector, int signo,
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int err_code, char *remcom_in_buffer,
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char *remcom_out_buffer,
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struct pt_regs *regs)
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{
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long addr;
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char *ptr;
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int newPC;
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int i;
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switch (remcom_in_buffer[0]) {
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case 'c':
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case 's':
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if (kgdb_contthread && kgdb_contthread != current) {
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strcpy(remcom_out_buffer, "E00");
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break;
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}
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kgdb_contthread = NULL;
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/* try to read optional parameter, pc unchanged if no parm */
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ptr = &remcom_in_buffer[1];
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if (kgdb_hex2long(&ptr, &addr)) {
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regs->retx = addr;
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}
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newPC = regs->retx;
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/* clear the trace bit */
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regs->syscfg &= 0xfffffffe;
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/* set the trace bit if we're stepping */
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if (remcom_in_buffer[0] == 's') {
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regs->syscfg |= 0x1;
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kgdb_single_step = regs->ipend;
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kgdb_single_step >>= 6;
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for (i = 10; i > 0; i--, kgdb_single_step >>= 1)
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if (kgdb_single_step & 1)
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break;
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/* i indicate event priority of current stopped instruction
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* user space instruction is 0, IVG15 is 1, IVTMR is 10.
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* kgdb_single_step > 0 means in single step mode
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*/
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kgdb_single_step = i + 1;
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preempt_disable();
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#ifdef CONFIG_IPIPE
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kgdb_arch_imask = cpu_pda[raw_smp_processor_id()].ex_imask;
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cpu_pda[raw_smp_processor_id()].ex_imask = 0;
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#endif
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}
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bfin_correct_hw_break();
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return 0;
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} /* switch */
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return -1; /* this means that we do not want to exit from the handler */
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}
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struct kgdb_arch arch_kgdb_ops = {
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.gdb_bpt_instr = {0xa1},
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.flags = KGDB_HW_BREAKPOINT,
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.set_hw_breakpoint = bfin_set_hw_break,
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.remove_hw_breakpoint = bfin_remove_hw_break,
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.disable_hw_break = bfin_disable_hw_debug,
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.remove_all_hw_break = bfin_remove_all_hw_break,
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.correct_hw_break = bfin_correct_hw_break,
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};
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#define IN_MEM(addr, size, l1_addr, l1_size) \
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({ \
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unsigned long __addr = (unsigned long)(addr); \
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(l1_size && __addr >= l1_addr && __addr + (size) <= l1_addr + l1_size); \
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})
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#define ASYNC_BANK_SIZE \
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(ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
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ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE)
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int kgdb_validate_break_address(unsigned long addr)
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{
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int cpu = raw_smp_processor_id();
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if (addr >= 0x1000 && (addr + BREAK_INSTR_SIZE) <= physical_mem_end)
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return 0;
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if (IN_MEM(addr, BREAK_INSTR_SIZE, ASYNC_BANK0_BASE, ASYNC_BANK_SIZE))
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return 0;
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if (cpu == 0 && IN_MEM(addr, BREAK_INSTR_SIZE, L1_CODE_START, L1_CODE_LENGTH))
|
|
return 0;
|
|
#ifdef CONFIG_SMP
|
|
else if (cpu == 1 && IN_MEM(addr, BREAK_INSTR_SIZE, COREB_L1_CODE_START, L1_CODE_LENGTH))
|
|
return 0;
|
|
#endif
|
|
if (IN_MEM(addr, BREAK_INSTR_SIZE, L2_START, L2_LENGTH))
|
|
return 0;
|
|
|
|
return -EFAULT;
|
|
}
|
|
|
|
void kgdb_arch_set_pc(struct pt_regs *regs, unsigned long ip)
|
|
{
|
|
regs->retx = ip;
|
|
}
|
|
|
|
int kgdb_arch_init(void)
|
|
{
|
|
kgdb_single_step = 0;
|
|
#ifdef CONFIG_IPIPE
|
|
kgdb_arch_imask = 0;
|
|
#endif
|
|
|
|
bfin_remove_all_hw_break();
|
|
return 0;
|
|
}
|
|
|
|
void kgdb_arch_exit(void)
|
|
{
|
|
}
|