356 lines
9.2 KiB
C
356 lines
9.2 KiB
C
/*
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* linux/arch/arm/common/it8152.c
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*
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* Copyright Compulab Ltd, 2002-2007
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* Mike Rapoport <mike@compulab.co.il>
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*
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* The DMA bouncing part is taken from arch/arm/mach-ixp4xx/common-pci.c
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* (see this file for respective copyrights)
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*
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* Thanks to Guennadi Liakhovetski <gl@dsa-ac.de> for IRQ enumberation
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* and demux code.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/ptrace.h>
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#include <linux/interrupt.h>
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#include <linux/mm.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/export.h>
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#include <asm/mach/pci.h>
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#include <asm/hardware/it8152.h>
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#define MAX_SLOTS 21
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static void it8152_mask_irq(struct irq_data *d)
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{
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unsigned int irq = d->irq;
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if (irq >= IT8152_LD_IRQ(0)) {
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__raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) |
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(1 << (irq - IT8152_LD_IRQ(0)))),
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IT8152_INTC_LDCNIMR);
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} else if (irq >= IT8152_LP_IRQ(0)) {
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__raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) |
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(1 << (irq - IT8152_LP_IRQ(0)))),
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IT8152_INTC_LPCNIMR);
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} else if (irq >= IT8152_PD_IRQ(0)) {
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__raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) |
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(1 << (irq - IT8152_PD_IRQ(0)))),
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IT8152_INTC_PDCNIMR);
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}
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}
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static void it8152_unmask_irq(struct irq_data *d)
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{
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unsigned int irq = d->irq;
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if (irq >= IT8152_LD_IRQ(0)) {
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__raw_writel((__raw_readl(IT8152_INTC_LDCNIMR) &
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~(1 << (irq - IT8152_LD_IRQ(0)))),
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IT8152_INTC_LDCNIMR);
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} else if (irq >= IT8152_LP_IRQ(0)) {
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__raw_writel((__raw_readl(IT8152_INTC_LPCNIMR) &
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~(1 << (irq - IT8152_LP_IRQ(0)))),
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IT8152_INTC_LPCNIMR);
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} else if (irq >= IT8152_PD_IRQ(0)) {
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__raw_writel((__raw_readl(IT8152_INTC_PDCNIMR) &
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~(1 << (irq - IT8152_PD_IRQ(0)))),
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IT8152_INTC_PDCNIMR);
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}
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}
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static struct irq_chip it8152_irq_chip = {
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.name = "it8152",
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.irq_ack = it8152_mask_irq,
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.irq_mask = it8152_mask_irq,
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.irq_unmask = it8152_unmask_irq,
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};
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void it8152_init_irq(void)
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{
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int irq;
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__raw_writel((0xffff), IT8152_INTC_PDCNIMR);
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__raw_writel((0), IT8152_INTC_PDCNIRR);
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__raw_writel((0xffff), IT8152_INTC_LPCNIMR);
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__raw_writel((0), IT8152_INTC_LPCNIRR);
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__raw_writel((0xffff), IT8152_INTC_LDCNIMR);
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__raw_writel((0), IT8152_INTC_LDCNIRR);
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for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
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irq_set_chip_and_handler(irq, &it8152_irq_chip,
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handle_level_irq);
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irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
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}
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}
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void it8152_irq_demux(struct irq_desc *desc)
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{
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int bits_pd, bits_lp, bits_ld;
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int i;
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while (1) {
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/* Read all */
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bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
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bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
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bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
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/* Ack */
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__raw_writel((~bits_pd), IT8152_INTC_PDCNIRR);
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__raw_writel((~bits_lp), IT8152_INTC_LPCNIRR);
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__raw_writel((~bits_ld), IT8152_INTC_LDCNIRR);
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if (!(bits_ld | bits_lp | bits_pd)) {
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/* Re-read to guarantee, that there was a moment of
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time, when they all three were 0. */
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bits_pd = __raw_readl(IT8152_INTC_PDCNIRR);
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bits_lp = __raw_readl(IT8152_INTC_LPCNIRR);
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bits_ld = __raw_readl(IT8152_INTC_LDCNIRR);
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if (!(bits_ld | bits_lp | bits_pd))
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return;
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}
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bits_pd &= ((1 << IT8152_PD_IRQ_COUNT) - 1);
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while (bits_pd) {
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i = __ffs(bits_pd);
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generic_handle_irq(IT8152_PD_IRQ(i));
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bits_pd &= ~(1 << i);
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}
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bits_lp &= ((1 << IT8152_LP_IRQ_COUNT) - 1);
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while (bits_lp) {
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i = __ffs(bits_lp);
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generic_handle_irq(IT8152_LP_IRQ(i));
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bits_lp &= ~(1 << i);
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}
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bits_ld &= ((1 << IT8152_LD_IRQ_COUNT) - 1);
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while (bits_ld) {
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i = __ffs(bits_ld);
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generic_handle_irq(IT8152_LD_IRQ(i));
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bits_ld &= ~(1 << i);
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}
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}
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}
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/* mapping for on-chip devices */
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int __init it8152_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
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(dev->device == PCI_DEVICE_ID_ITE_8152)) {
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if ((dev->class >> 8) == PCI_CLASS_MULTIMEDIA_AUDIO)
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return IT8152_AUDIO_INT;
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if ((dev->class >> 8) == PCI_CLASS_SERIAL_USB)
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return IT8152_USB_INT;
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if ((dev->class >> 8) == PCI_CLASS_SYSTEM_DMA)
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return IT8152_CDMA_INT;
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}
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return 0;
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}
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static unsigned long it8152_pci_dev_base_address(struct pci_bus *bus,
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unsigned int devfn)
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{
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unsigned long addr = 0;
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if (bus->number == 0) {
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if (devfn < PCI_DEVFN(MAX_SLOTS, 0))
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addr = (devfn << 8);
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} else
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addr = (bus->number << 16) | (devfn << 8);
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return addr;
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}
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static int it8152_pci_read_config(struct pci_bus *bus,
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unsigned int devfn, int where,
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int size, u32 *value)
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{
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unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
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u32 v;
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int shift;
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shift = (where & 3);
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__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
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v = (__raw_readl(IT8152_PCI_CFG_DATA) >> (8 * (shift)));
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*value = v;
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return PCIBIOS_SUCCESSFUL;
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}
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static int it8152_pci_write_config(struct pci_bus *bus,
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unsigned int devfn, int where,
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int size, u32 value)
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{
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unsigned long addr = it8152_pci_dev_base_address(bus, devfn);
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u32 v, vtemp, mask = 0;
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int shift;
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if (size == 1)
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mask = 0xff;
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if (size == 2)
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mask = 0xffff;
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shift = (where & 3);
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__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
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vtemp = __raw_readl(IT8152_PCI_CFG_DATA);
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if (mask)
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vtemp &= ~(mask << (8 * shift));
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else
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vtemp = 0;
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v = (value << (8 * shift));
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__raw_writel((addr + where), IT8152_PCI_CFG_ADDR);
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__raw_writel((v | vtemp), IT8152_PCI_CFG_DATA);
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops it8152_ops = {
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.read = it8152_pci_read_config,
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.write = it8152_pci_write_config,
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};
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static struct resource it8152_io = {
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.name = "IT8152 PCI I/O region",
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.flags = IORESOURCE_IO,
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};
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static struct resource it8152_mem = {
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.name = "IT8152 PCI memory region",
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.start = 0x10000000,
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.end = 0x13e00000,
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.flags = IORESOURCE_MEM,
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};
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/*
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* The following functions are needed for DMA bouncing.
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* ITE8152 chip can address up to 64MByte, so all the devices
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* connected to ITE8152 (PCI and USB) should have limited DMA window
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*/
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static int it8152_needs_bounce(struct device *dev, dma_addr_t dma_addr, size_t size)
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{
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dev_dbg(dev, "%s: dma_addr %08x, size %08x\n",
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__func__, dma_addr, size);
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return (dma_addr + size - PHYS_OFFSET) >= SZ_64M;
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}
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/*
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* Setup DMA mask to 64MB on devices connected to ITE8152. Ignore all
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* other devices.
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*/
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static int it8152_pci_platform_notify(struct device *dev)
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{
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if (dev_is_pci(dev)) {
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if (dev->dma_mask)
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*dev->dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
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dev->coherent_dma_mask = (SZ_64M - 1) | PHYS_OFFSET;
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dmabounce_register_dev(dev, 2048, 4096, it8152_needs_bounce);
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}
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return 0;
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}
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static int it8152_pci_platform_notify_remove(struct device *dev)
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{
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if (dev_is_pci(dev))
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dmabounce_unregister_dev(dev);
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return 0;
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}
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int dma_set_coherent_mask(struct device *dev, u64 mask)
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{
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if (mask >= PHYS_OFFSET + SZ_64M - 1)
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return 0;
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return -EIO;
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}
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int __init it8152_pci_setup(int nr, struct pci_sys_data *sys)
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{
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/*
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* FIXME: use pci_ioremap_io to remap the IO space here and
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* move over to the generic io.h implementation.
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* This requires solving the same problem for PXA PCMCIA
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* support.
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*/
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it8152_io.start = (unsigned long)IT8152_IO_BASE + 0x12000;
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it8152_io.end = (unsigned long)IT8152_IO_BASE + 0x12000 + 0x100000;
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sys->mem_offset = 0x10000000;
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sys->io_offset = (unsigned long)IT8152_IO_BASE;
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if (request_resource(&ioport_resource, &it8152_io)) {
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printk(KERN_ERR "PCI: unable to allocate IO region\n");
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goto err0;
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}
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if (request_resource(&iomem_resource, &it8152_mem)) {
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printk(KERN_ERR "PCI: unable to allocate memory region\n");
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goto err1;
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}
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pci_add_resource_offset(&sys->resources, &it8152_io, sys->io_offset);
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pci_add_resource_offset(&sys->resources, &it8152_mem, sys->mem_offset);
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if (platform_notify || platform_notify_remove) {
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printk(KERN_ERR "PCI: Can't use platform_notify\n");
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goto err2;
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}
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platform_notify = it8152_pci_platform_notify;
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platform_notify_remove = it8152_pci_platform_notify_remove;
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return 1;
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err2:
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release_resource(&it8152_io);
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err1:
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release_resource(&it8152_mem);
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err0:
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return -EBUSY;
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}
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/* ITE bridge requires setting latency timer to avoid early bus access
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termination by PCI bus master devices
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*/
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void pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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/* no need to update on-chip OHCI controller */
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if ((dev->vendor == PCI_VENDOR_ID_ITE) &&
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(dev->device == PCI_DEVICE_ID_ITE_8152) &&
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((dev->class >> 8) == PCI_CLASS_SERIAL_USB))
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return;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat < 16)
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lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
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else if (lat > pcibios_max_latency)
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lat = pcibios_max_latency;
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else
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return;
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printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n",
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pci_name(dev), lat);
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
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}
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EXPORT_SYMBOL(dma_set_coherent_mask);
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