671 lines
18 KiB
Plaintext
671 lines
18 KiB
Plaintext
/*
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* Device Tree Source for the r7s72100 SoC
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*
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* Copyright (C) 2013-14 Renesas Solutions Corp.
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* Copyright (C) 2014 Wolfram Sang, Sang Engineering <wsa@sang-engineering.com>
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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#include <dt-bindings/clock/r7s72100-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "renesas,r7s72100";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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spi0 = &spi0;
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spi1 = &spi1;
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spi2 = &spi2;
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spi3 = &spi3;
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spi4 = &spi4;
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};
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clocks {
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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/* External clocks */
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extal_clk: extal {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* If clk present, value must be set by board */
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clock-frequency = <0>;
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};
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usb_x1_clk: usb_x1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* If clk present, value must be set by board */
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clock-frequency = <0>;
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};
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rtc_x1_clk: rtc_x1 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* If clk present, value must be set by board to 32678 */
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clock-frequency = <0>;
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};
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rtc_x3_clk: rtc_x3 {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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/* If clk present, value must be set by board to 4000000 */
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clock-frequency = <0>;
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};
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/* Fixed factor clocks */
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b_clk: b {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R7S72100_CLK_PLL>;
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clock-mult = <1>;
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clock-div = <3>;
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};
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p1_clk: p1 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R7S72100_CLK_PLL>;
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clock-mult = <1>;
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clock-div = <6>;
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};
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p0_clk: p0 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&cpg_clocks R7S72100_CLK_PLL>;
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clock-mult = <1>;
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clock-div = <12>;
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};
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/* Special CPG clocks */
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cpg_clocks: cpg_clocks@fcfe0000 {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-cpg-clocks",
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"renesas,rz-cpg-clocks";
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reg = <0xfcfe0000 0x18>;
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clocks = <&extal_clk>, <&usb_x1_clk>;
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clock-output-names = "pll", "i", "g";
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#power-domain-cells = <0>;
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};
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/* MSTP clocks */
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mstp3_clks: mstp3_clks@fcfe0420 {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xfcfe0420 4>;
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clocks = <&p0_clk>;
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clock-indices = <R7S72100_CLK_MTU2>;
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clock-output-names = "mtu2";
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};
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mstp4_clks: mstp4_clks@fcfe0424 {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xfcfe0424 4>;
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clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
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<&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
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clock-indices = <
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R7S72100_CLK_SCIF0 R7S72100_CLK_SCIF1 R7S72100_CLK_SCIF2 R7S72100_CLK_SCIF3
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R7S72100_CLK_SCIF4 R7S72100_CLK_SCIF5 R7S72100_CLK_SCIF6 R7S72100_CLK_SCIF7
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>;
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clock-output-names = "scif0", "scif1", "scif2", "scif3", "scif4", "scif5", "scif6", "scif7";
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};
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mstp5_clks: mstp5_clks@fcfe0428 {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xfcfe0428 4>;
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clocks = <&p0_clk>, <&p0_clk>;
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clock-indices = <R7S72100_CLK_OSTM0 R7S72100_CLK_OSTM1>;
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clock-output-names = "ostm0", "ostm1";
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};
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mstp6_clks: mstp6_clks@fcfe042c {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xfcfe042c 4>;
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clocks = <&p0_clk>;
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clock-indices = <R7S72100_CLK_RTC>;
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clock-output-names = "rtc";
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};
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mstp7_clks: mstp7_clks@fcfe0430 {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xfcfe0430 4>;
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clocks = <&b_clk>, <&p1_clk>, <&p1_clk>;
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clock-indices = <R7S72100_CLK_ETHER R7S72100_CLK_USB0 R7S72100_CLK_USB1>;
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clock-output-names = "ether", "usb0", "usb1";
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};
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mstp8_clks: mstp8_clks@fcfe0434 {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xfcfe0434 4>;
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clocks = <&p1_clk>;
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clock-indices = <R7S72100_CLK_MMCIF>;
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clock-output-names = "mmcif";
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};
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mstp9_clks: mstp9_clks@fcfe0438 {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xfcfe0438 4>;
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clocks = <&p0_clk>, <&p0_clk>, <&p0_clk>, <&p0_clk>;
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clock-indices = <
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R7S72100_CLK_I2C0 R7S72100_CLK_I2C1 R7S72100_CLK_I2C2 R7S72100_CLK_I2C3
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>;
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clock-output-names = "i2c0", "i2c1", "i2c2", "i2c3";
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};
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mstp10_clks: mstp10_clks@fcfe043c {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xfcfe043c 4>;
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clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>,
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<&p1_clk>;
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clock-indices = <
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R7S72100_CLK_SPI0 R7S72100_CLK_SPI1 R7S72100_CLK_SPI2 R7S72100_CLK_SPI3
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R7S72100_CLK_SPI4
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>;
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clock-output-names = "spi0", "spi1", "spi2", "spi3", "spi4";
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};
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mstp12_clks: mstp12_clks@fcfe0444 {
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#clock-cells = <1>;
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compatible = "renesas,r7s72100-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0xfcfe0444 4>;
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clocks = <&p1_clk>, <&p1_clk>, <&p1_clk>, <&p1_clk>;
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clock-indices = <
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R7S72100_CLK_SDHI00 R7S72100_CLK_SDHI01
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R7S72100_CLK_SDHI10 R7S72100_CLK_SDHI11
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>;
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clock-output-names = "sdhi00", "sdhi01", "sdhi10", "sdhi11";
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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clock-frequency = <400000000>;
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clocks = <&cpg_clocks R7S72100_CLK_I>;
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next-level-cache = <&L2>;
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};
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};
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pinctrl: pin-controller@fcfe3000 {
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compatible = "renesas,r7s72100-ports";
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reg = <0xfcfe3000 0x4230>;
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port0: gpio-0 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 0 6>;
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};
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port1: gpio-1 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 16 16>;
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};
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port2: gpio-2 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 32 16>;
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};
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port3: gpio-3 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 48 16>;
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};
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port4: gpio-4 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 64 16>;
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};
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port5: gpio-5 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 80 11>;
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};
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port6: gpio-6 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 96 16>;
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};
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port7: gpio-7 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 112 16>;
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};
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port8: gpio-8 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 128 16>;
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};
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port9: gpio-9 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 144 8>;
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};
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port10: gpio-10 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 160 16>;
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};
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port11: gpio-11 {
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl 0 176 16>;
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};
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};
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scif0: serial@e8007000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8007000 64>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF0>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif1: serial@e8007800 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8007800 64>;
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interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF1>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif2: serial@e8008000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8008000 64>;
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interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF2>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif3: serial@e8008800 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8008800 64>;
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interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF3>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif4: serial@e8009000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8009000 64>;
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interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF4>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif5: serial@e8009800 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe8009800 64>;
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interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF5>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif6: serial@e800a000 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe800a000 64>;
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interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF6>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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scif7: serial@e800a800 {
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compatible = "renesas,scif-r7s72100", "renesas,scif";
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reg = <0xe800a800 64>;
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interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp4_clks R7S72100_CLK_SCIF7>;
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clock-names = "fck";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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spi0: spi@e800c800 {
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compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
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reg = <0xe800c800 0x24>;
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interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI0>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi1: spi@e800d000 {
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compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
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reg = <0xe800d000 0x24>;
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interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI1>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi2: spi@e800d800 {
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compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
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reg = <0xe800d800 0x24>;
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interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "error", "rx", "tx";
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clocks = <&mstp10_clks R7S72100_CLK_SPI2>;
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power-domains = <&cpg_clocks>;
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num-cs = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spi3: spi@e800e000 {
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compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
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reg = <0xe800e000 0x24>;
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interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error", "rx", "tx";
|
|
clocks = <&mstp10_clks R7S72100_CLK_SPI3>;
|
|
power-domains = <&cpg_clocks>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi4: spi@e800e800 {
|
|
compatible = "renesas,rspi-r7s72100", "renesas,rspi-rz";
|
|
reg = <0xe800e800 0x24>;
|
|
interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error", "rx", "tx";
|
|
clocks = <&mstp10_clks R7S72100_CLK_SPI4>;
|
|
power-domains = <&cpg_clocks>;
|
|
num-cs = <1>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@e8201000 {
|
|
compatible = "arm,pl390";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0xe8201000 0x1000>,
|
|
<0xe8202000 0x1000>;
|
|
};
|
|
|
|
L2: cache-controller@3ffff000 {
|
|
compatible = "arm,pl310-cache";
|
|
reg = <0x3ffff000 0x1000>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
arm,early-bresp-disable;
|
|
arm,full-line-zero-disable;
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
};
|
|
|
|
wdt: watchdog@fcfe0000 {
|
|
compatible = "renesas,r7s72100-wdt", "renesas,rza-wdt";
|
|
reg = <0xfcfe0000 0x6>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&p0_clk>;
|
|
};
|
|
|
|
i2c0: i2c@fcfee000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
|
|
reg = <0xfcfee000 0x44>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R7S72100_CLK_I2C0>;
|
|
clock-frequency = <100000>;
|
|
power-domains = <&cpg_clocks>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@fcfee400 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
|
|
reg = <0xfcfee400 0x44>;
|
|
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 167 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R7S72100_CLK_I2C1>;
|
|
clock-frequency = <100000>;
|
|
power-domains = <&cpg_clocks>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@fcfee800 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
|
|
reg = <0xfcfee800 0x44>;
|
|
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 174 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 175 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R7S72100_CLK_I2C2>;
|
|
clock-frequency = <100000>;
|
|
power-domains = <&cpg_clocks>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@fcfeec00 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,riic-r7s72100", "renesas,riic-rz";
|
|
reg = <0xfcfeec00 0x44>;
|
|
interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 182 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
|
|
<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp9_clks R7S72100_CLK_I2C3>;
|
|
clock-frequency = <100000>;
|
|
power-domains = <&cpg_clocks>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mtu2: timer@fcff0000 {
|
|
compatible = "renesas,mtu2-r7s72100", "renesas,mtu2";
|
|
reg = <0xfcff0000 0x400>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "tgi0a";
|
|
clocks = <&mstp3_clks R7S72100_CLK_MTU2>;
|
|
clock-names = "fck";
|
|
power-domains = <&cpg_clocks>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ether: ethernet@e8203000 {
|
|
compatible = "renesas,ether-r7s72100";
|
|
reg = <0xe8203000 0x800>,
|
|
<0xe8204800 0x200>;
|
|
interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp7_clks R7S72100_CLK_ETHER>;
|
|
power-domains = <&cpg_clocks>;
|
|
phy-mode = "mii";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
mmcif: mmc@e804c800 {
|
|
compatible = "renesas,mmcif-r7s72100", "renesas,sh-mmcif";
|
|
reg = <0xe804c800 0x80>;
|
|
interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&mstp8_clks R7S72100_CLK_MMCIF>;
|
|
power-domains = <&cpg_clocks>;
|
|
reg-io-width = <4>;
|
|
bus-width = <8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi0: sd@e804e000 {
|
|
compatible = "renesas,sdhi-r7s72100";
|
|
reg = <0xe804e000 0x100>;
|
|
interrupts = <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&mstp12_clks R7S72100_CLK_SDHI00>,
|
|
<&mstp12_clks R7S72100_CLK_SDHI01>;
|
|
clock-names = "core", "cd";
|
|
power-domains = <&cpg_clocks>;
|
|
cap-sd-highspeed;
|
|
cap-sdio-irq;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi1: sd@e804e800 {
|
|
compatible = "renesas,sdhi-r7s72100";
|
|
reg = <0xe804e800 0x100>;
|
|
interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH
|
|
GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
clocks = <&mstp12_clks R7S72100_CLK_SDHI10>,
|
|
<&mstp12_clks R7S72100_CLK_SDHI11>;
|
|
clock-names = "core", "cd";
|
|
power-domains = <&cpg_clocks>;
|
|
cap-sd-highspeed;
|
|
cap-sdio-irq;
|
|
status = "disabled";
|
|
};
|
|
|
|
ostm0: timer@fcfec000 {
|
|
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
|
|
reg = <0xfcfec000 0x30>;
|
|
interrupts = <GIC_SPI 102 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&mstp5_clks R7S72100_CLK_OSTM0>;
|
|
power-domains = <&cpg_clocks>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ostm1: timer@fcfec400 {
|
|
compatible = "renesas,r7s72100-ostm", "renesas,ostm";
|
|
reg = <0xfcfec400 0x30>;
|
|
interrupts = <GIC_SPI 103 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&mstp5_clks R7S72100_CLK_OSTM1>;
|
|
power-domains = <&cpg_clocks>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc: rtc@fcff1000 {
|
|
compatible = "renesas,r7s72100-rtc", "renesas,sh-rtc";
|
|
reg = <0xfcff1000 0x2e>;
|
|
interrupts = <GIC_SPI 276 IRQ_TYPE_EDGE_RISING
|
|
GIC_SPI 277 IRQ_TYPE_EDGE_RISING
|
|
GIC_SPI 278 IRQ_TYPE_EDGE_RISING>;
|
|
interrupt-names = "alarm", "period", "carry";
|
|
clocks = <&mstp6_clks R7S72100_CLK_RTC>, <&rtc_x1_clk>,
|
|
<&rtc_x3_clk>, <&extal_clk>;
|
|
clock-names = "fck", "rtc_x1", "rtc_x3", "extal";
|
|
power-domains = <&cpg_clocks>;
|
|
status = "disabled";
|
|
};
|
|
};
|