135 lines
4.5 KiB
Plaintext
135 lines
4.5 KiB
Plaintext
* Broadcom iProc PCIe controller with the platform bus interface
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Required properties:
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- compatible:
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"brcm,iproc-pcie" for the first generation of PAXB based controller,
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used in SoCs including NSP, Cygnus, NS2, and Pegasus
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"brcm,iproc-pcie-paxb-v2" for the second generation of PAXB-based
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controllers, used in Stingray
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"brcm,iproc-pcie-paxc" for the first generation of PAXC based
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controller, used in NS2
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"brcm,iproc-pcie-paxc-v2" for the second generation of PAXC based
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controller, used in Stingray
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PAXB-based root complex is used for external endpoint devices. PAXC-based
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root complex is connected to emulated endpoint devices internal to the ASIC
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- reg: base address and length of the PCIe controller I/O register space
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- #interrupt-cells: set to <1>
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- interrupt-map-mask and interrupt-map, standard PCI properties to define the
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mapping of the PCIe interface to interrupt numbers
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- linux,pci-domain: PCI domain ID. Should be unique for each host controller
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- bus-range: PCI bus numbers covered
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions
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Optional properties:
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- phys: phandle of the PCIe PHY device
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- phy-names: must be "pcie-phy"
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- dma-coherent: present if DMA operations are coherent
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- dma-ranges: Some PAXB-based root complexes do not have inbound mapping done
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by the ASIC after power on reset. In this case, SW is required to configure
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the mapping, based on inbound memory regions specified by this property.
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- brcm,pcie-ob: Some iProc SoCs do not have the outbound address mapping done
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by the ASIC after power on reset. In this case, SW needs to configure it
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If the brcm,pcie-ob property is present, the following properties become
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effective:
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Required:
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- brcm,pcie-ob-axi-offset: The offset from the AXI address to the internal
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address used by the iProc PCIe core (not the PCIe address)
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MSI support (optional):
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For older platforms without MSI integrated in the GIC, iProc PCIe core provides
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an event queue based MSI support. The iProc MSI uses host memories to store
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MSI posted writes in the event queues
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On newer iProc platforms, gicv2m or gicv3-its based MSI support should be used
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- msi-map: Maps a Requester ID to an MSI controller and associated MSI
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sideband data
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- msi-parent: Link to the device node of the MSI controller, used when no MSI
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sideband data is passed between the iProc PCIe controller and the MSI
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controller
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Refer to the following binding documents for more detailed description on
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the use of 'msi-map' and 'msi-parent':
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Documentation/devicetree/bindings/pci/pci-msi.txt
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Documentation/devicetree/bindings/interrupt-controller/msi.txt
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When the iProc event queue based MSI is used, one needs to define the
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following properties in the MSI device node:
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- compatible: Must be "brcm,iproc-msi"
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- msi-controller: claims itself as an MSI controller
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- interrupt-parent: Link to its parent interrupt device
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- interrupts: List of interrupt IDs from its parent interrupt device
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Optional properties:
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- brcm,pcie-msi-inten: Needs to be present for some older iProc platforms that
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require the interrupt enable registers to be set explicitly to enable MSI
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Example:
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pcie0: pcie@18012000 {
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compatible = "brcm,iproc-pcie";
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reg = <0x18012000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 100 IRQ_TYPE_NONE>;
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x28000000 0 0x00010000
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0x82000000 0 0x20000000 0x20000000 0 0x04000000>;
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phys = <&phy 0 5>;
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phy-names = "pcie-phy";
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brcm,pcie-ob;
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brcm,pcie-ob-axi-offset = <0x00000000>;
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msi-parent = <&msi0>;
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/* iProc event queue based MSI */
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msi0: msi@18012000 {
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compatible = "brcm,iproc-msi";
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msi-controller;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 96 IRQ_TYPE_NONE>,
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<GIC_SPI 97 IRQ_TYPE_NONE>,
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<GIC_SPI 98 IRQ_TYPE_NONE>,
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<GIC_SPI 99 IRQ_TYPE_NONE>,
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};
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};
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pcie1: pcie@18013000 {
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compatible = "brcm,iproc-pcie";
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reg = <0x18013000 0x1000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 106 IRQ_TYPE_NONE>;
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linux,pci-domain = <1>;
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bus-range = <0x00 0xff>;
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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ranges = <0x81000000 0 0 0x48000000 0 0x00010000
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0x82000000 0 0x40000000 0x40000000 0 0x04000000>;
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phys = <&phy 1 6>;
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phy-names = "pcie-phy";
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};
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