126 lines
3.7 KiB
Plaintext
126 lines
3.7 KiB
Plaintext
Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
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Reference
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[1] Si5351A/B/C Data Sheet
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http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
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The Si5351a/b/c are programmable i2c clock generators with up to 8 output
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clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
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3 output clocks are accessible. The internal structure of the clock
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generators can be found in [1].
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==I2C device node==
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Required properties:
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- compatible: shall be one of the following:
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"silabs,si5351a" - Si5351a, QFN20 package
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"silabs,si5351a-msop" - Si5351a, MSOP10 package
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"silabs,si5351b" - Si5351b, QFN20 package
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"silabs,si5351c" - Si5351c, QFN20 package
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- reg: i2c device address, shall be 0x60 or 0x61.
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- #clock-cells: from common clock binding; shall be set to 1.
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- clocks: from common clock binding; list of parent clock
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handles, shall be xtal reference clock or xtal and clkin for
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si5351c only. Corresponding clock input names are "xtal" and
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"clkin" respectively.
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- #address-cells: shall be set to 1.
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- #size-cells: shall be set to 0.
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Optional properties:
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- silabs,pll-source: pair of (number, source) for each pll. Allows
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to overwrite clock source of pll A (number=0) or B (number=1).
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==Child nodes==
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Each of the clock outputs can be overwritten individually by
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using a child node to the I2C device node. If a child node for a clock
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output is not set, the eeprom configuration is not overwritten.
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Required child node properties:
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- reg: number of clock output.
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Optional child node properties:
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- silabs,clock-source: source clock of the output divider stage N, shall be
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0 = multisynth N
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1 = multisynth 0 for output clocks 0-3, else multisynth4
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2 = xtal
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3 = clkin (si5351c only)
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- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
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- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
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divider.
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- silabs,pll-master: boolean, multisynth can change pll frequency.
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- silabs,disable-state : clock output disable state, shall be
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0 = clock output is driven LOW when disabled
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1 = clock output is driven HIGH when disabled
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2 = clock output is FLOATING (HIGH-Z) when disabled
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3 = clock output is NEVER disabled
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==Example==
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/* 25MHz reference crystal */
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ref25: ref25M {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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};
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i2c-master-node {
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/* Si5351a msop10 i2c clock generator */
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si5351a: clock-generator@60 {
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compatible = "silabs,si5351a-msop";
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reg = <0x60>;
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#address-cells = <1>;
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#size-cells = <0>;
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#clock-cells = <1>;
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/* connect xtal input to 25MHz reference */
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clocks = <&ref25>;
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clock-names = "xtal";
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/* connect xtal input as source of pll0 and pll1 */
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silabs,pll-source = <0 0>, <1 0>;
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/*
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* overwrite clkout0 configuration with:
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* - 8mA output drive strength
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* - pll0 as clock source of multisynth0
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* - multisynth0 as clock source of output divider
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* - multisynth0 can change pll0
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* - set initial clock frequency of 74.25MHz
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*/
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clkout0 {
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reg = <0>;
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silabs,drive-strength = <8>;
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silabs,multisynth-source = <0>;
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silabs,clock-source = <0>;
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silabs,pll-master;
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clock-frequency = <74250000>;
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};
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/*
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* overwrite clkout1 configuration with:
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* - 4mA output drive strength
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* - pll1 as clock source of multisynth1
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* - multisynth1 as clock source of output divider
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* - multisynth1 can change pll1
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*/
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clkout1 {
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reg = <1>;
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silabs,drive-strength = <4>;
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silabs,multisynth-source = <1>;
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silabs,clock-source = <0>;
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pll-master;
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};
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/*
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* overwrite clkout2 configuration with:
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* - xtal as clock source of output divider
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*/
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clkout2 {
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reg = <2>;
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silabs,clock-source = <2>;
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};
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};
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};
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