54 lines
1.8 KiB
Plaintext
54 lines
1.8 KiB
Plaintext
* Samsung Audio Subsystem Clock Controller
|
|
|
|
The Samsung Audio Subsystem clock controller generates and supplies clocks
|
|
to Audio Subsystem block available in the S5PV210 and compatible SoCs.
|
|
|
|
Required Properties:
|
|
|
|
- compatible: should be "samsung,s5pv210-audss-clock".
|
|
- reg: physical base address and length of the controller's register set.
|
|
|
|
- #clock-cells: should be 1.
|
|
|
|
- clocks:
|
|
- hclk: AHB bus clock of the Audio Subsystem.
|
|
- xxti: Optional fixed rate PLL reference clock, parent of mout_audss. If
|
|
not specified (i.e. xusbxti is used for PLL reference), it is fixed to
|
|
a clock named "xxti".
|
|
- fout_epll: Input PLL to the AudioSS block, parent of mout_audss.
|
|
- iiscdclk0: Optional external i2s clock, parent of mout_i2s. If not
|
|
specified, it is fixed to a clock named "iiscdclk0".
|
|
- sclk_audio0: Audio bus clock, parent of mout_i2s.
|
|
|
|
- clock-names: Aliases for the above clocks. They should be "hclk",
|
|
"xxti", "fout_epll", "iiscdclk0", and "sclk_audio0" respectively.
|
|
|
|
All available clocks are defined as preprocessor macros in
|
|
dt-bindings/clock/s5pv210-audss-clk.h header and can be used in device
|
|
tree sources.
|
|
|
|
Example: Clock controller node.
|
|
|
|
clk_audss: clock-controller@c0900000 {
|
|
compatible = "samsung,s5pv210-audss-clock";
|
|
reg = <0xc0900000 0x1000>;
|
|
#clock-cells = <1>;
|
|
clock-names = "hclk", "xxti",
|
|
"fout_epll", "sclk_audio0";
|
|
clocks = <&clocks DOUT_HCLKP>, <&xxti>,
|
|
<&clocks FOUT_EPLL>, <&clocks SCLK_AUDIO0>;
|
|
};
|
|
|
|
Example: I2S controller node that consumes the clock generated by the clock
|
|
controller. Refer to the standard clock bindings for information
|
|
about 'clocks' and 'clock-names' property.
|
|
|
|
i2s0: i2s@3830000 {
|
|
/* ... */
|
|
clock-names = "iis", "i2s_opclk0",
|
|
"i2s_opclk1";
|
|
clocks = <&clk_audss CLK_I2S>, <&clk_audss CLK_I2S>,
|
|
<&clk_audss CLK_DOUT_AUD_BUS>;
|
|
/* ... */
|
|
};
|