319 lines
9.0 KiB
C
319 lines
9.0 KiB
C
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/*
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* Universal Interface for Intel High Definition Audio Codec
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*
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* HD audio interface patch for Silicon Labs 3054/5 modem codec
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*
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* Copyright (c) 2005 Sasha Khapyorsky <sashak@alsa-project.org>
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* Takashi Iwai <tiwai@suse.de>
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*
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*
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* This driver is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This driver is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <sound/core.h>
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#include "hda_codec.h"
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#include "hda_local.h"
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/* si3054 verbs */
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#define SI3054_VERB_READ_NODE 0x900
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#define SI3054_VERB_WRITE_NODE 0x100
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/* si3054 nodes (registers) */
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#define SI3054_EXTENDED_MID 2
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#define SI3054_LINE_RATE 3
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#define SI3054_LINE_LEVEL 4
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#define SI3054_GPIO_CFG 5
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#define SI3054_GPIO_POLARITY 6
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#define SI3054_GPIO_STICKY 7
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#define SI3054_GPIO_WAKEUP 8
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#define SI3054_GPIO_STATUS 9
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#define SI3054_GPIO_CONTROL 10
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#define SI3054_MISC_AFE 11
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#define SI3054_CHIPID 12
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#define SI3054_LINE_CFG1 13
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#define SI3054_LINE_STATUS 14
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#define SI3054_DC_TERMINATION 15
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#define SI3054_LINE_CONFIG 16
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#define SI3054_CALLPROG_ATT 17
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#define SI3054_SQ_CONTROL 18
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#define SI3054_MISC_CONTROL 19
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#define SI3054_RING_CTRL1 20
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#define SI3054_RING_CTRL2 21
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/* extended MID */
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#define SI3054_MEI_READY 0xf
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/* line level */
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#define SI3054_ATAG_MASK 0x00f0
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#define SI3054_DTAG_MASK 0xf000
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/* GPIO bits */
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#define SI3054_GPIO_OH 0x0001
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#define SI3054_GPIO_CID 0x0002
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/* chipid and revisions */
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#define SI3054_CHIPID_CODEC_REV_MASK 0x000f
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#define SI3054_CHIPID_DAA_REV_MASK 0x00f0
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#define SI3054_CHIPID_INTERNATIONAL 0x0100
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#define SI3054_CHIPID_DAA_ID 0x0f00
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#define SI3054_CHIPID_CODEC_ID (1<<12)
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/* si3054 codec registers (nodes) access macros */
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#define GET_REG(codec,reg) (snd_hda_codec_read(codec,reg,0,SI3054_VERB_READ_NODE,0))
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#define SET_REG(codec,reg,val) (snd_hda_codec_write(codec,reg,0,SI3054_VERB_WRITE_NODE,val))
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#define SET_REG_CACHE(codec,reg,val) \
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snd_hda_codec_write_cache(codec,reg,0,SI3054_VERB_WRITE_NODE,val)
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struct si3054_spec {
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unsigned international;
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};
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/*
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* Modem mixer
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*/
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#define PRIVATE_VALUE(reg,mask) ((reg<<16)|(mask&0xffff))
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#define PRIVATE_REG(val) ((val>>16)&0xffff)
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#define PRIVATE_MASK(val) (val&0xffff)
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#define si3054_switch_info snd_ctl_boolean_mono_info
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static int si3054_switch_get(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *uvalue)
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{
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struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
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u16 reg = PRIVATE_REG(kcontrol->private_value);
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u16 mask = PRIVATE_MASK(kcontrol->private_value);
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uvalue->value.integer.value[0] = (GET_REG(codec, reg)) & mask ? 1 : 0 ;
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return 0;
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}
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static int si3054_switch_put(struct snd_kcontrol *kcontrol,
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struct snd_ctl_elem_value *uvalue)
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{
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struct hda_codec *codec = snd_kcontrol_chip(kcontrol);
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u16 reg = PRIVATE_REG(kcontrol->private_value);
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u16 mask = PRIVATE_MASK(kcontrol->private_value);
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if (uvalue->value.integer.value[0])
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SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) | mask);
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else
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SET_REG_CACHE(codec, reg, (GET_REG(codec, reg)) & ~mask);
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return 0;
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}
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#define SI3054_KCONTROL(kname,reg,mask) { \
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.iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
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.name = kname, \
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.subdevice = HDA_SUBDEV_NID_FLAG | reg, \
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.info = si3054_switch_info, \
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.get = si3054_switch_get, \
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.put = si3054_switch_put, \
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.private_value = PRIVATE_VALUE(reg,mask), \
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}
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static const struct snd_kcontrol_new si3054_modem_mixer[] = {
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SI3054_KCONTROL("Off-hook Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_OH),
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SI3054_KCONTROL("Caller ID Switch", SI3054_GPIO_CONTROL, SI3054_GPIO_CID),
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{}
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};
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static int si3054_build_controls(struct hda_codec *codec)
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{
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return snd_hda_add_new_ctls(codec, si3054_modem_mixer);
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}
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/*
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* PCM callbacks
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*/
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static int si3054_pcm_prepare(struct hda_pcm_stream *hinfo,
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struct hda_codec *codec,
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unsigned int stream_tag,
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unsigned int format,
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struct snd_pcm_substream *substream)
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{
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u16 val;
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SET_REG(codec, SI3054_LINE_RATE, substream->runtime->rate);
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val = GET_REG(codec, SI3054_LINE_LEVEL);
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val &= 0xff << (8 * (substream->stream != SNDRV_PCM_STREAM_PLAYBACK));
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val |= ((stream_tag & 0xf) << 4) << (8 * (substream->stream == SNDRV_PCM_STREAM_PLAYBACK));
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SET_REG(codec, SI3054_LINE_LEVEL, val);
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snd_hda_codec_setup_stream(codec, hinfo->nid,
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stream_tag, 0, format);
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return 0;
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}
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static int si3054_pcm_open(struct hda_pcm_stream *hinfo,
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struct hda_codec *codec,
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struct snd_pcm_substream *substream)
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{
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static const unsigned int rates[] = { 8000, 9600, 16000 };
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static const struct snd_pcm_hw_constraint_list hw_constraints_rates = {
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.count = ARRAY_SIZE(rates),
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.list = rates,
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.mask = 0,
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};
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substream->runtime->hw.period_bytes_min = 80;
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return snd_pcm_hw_constraint_list(substream->runtime, 0,
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SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates);
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}
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static const struct hda_pcm_stream si3054_pcm = {
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.substreams = 1,
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.channels_min = 1,
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.channels_max = 1,
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.nid = 0x1,
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.rates = SNDRV_PCM_RATE_8000|SNDRV_PCM_RATE_16000|SNDRV_PCM_RATE_KNOT,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,
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.maxbps = 16,
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.ops = {
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.open = si3054_pcm_open,
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.prepare = si3054_pcm_prepare,
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},
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};
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static int si3054_build_pcms(struct hda_codec *codec)
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{
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struct hda_pcm *info;
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info = snd_hda_codec_pcm_new(codec, "Si3054 Modem");
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if (!info)
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return -ENOMEM;
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info->stream[SNDRV_PCM_STREAM_PLAYBACK] = si3054_pcm;
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info->stream[SNDRV_PCM_STREAM_CAPTURE] = si3054_pcm;
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info->stream[SNDRV_PCM_STREAM_PLAYBACK].nid = codec->core.mfg;
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info->stream[SNDRV_PCM_STREAM_CAPTURE].nid = codec->core.mfg;
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info->pcm_type = HDA_PCM_TYPE_MODEM;
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return 0;
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}
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/*
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* Init part
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*/
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static int si3054_init(struct hda_codec *codec)
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{
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struct si3054_spec *spec = codec->spec;
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unsigned wait_count;
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u16 val;
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if (snd_hdac_regmap_add_vendor_verb(&codec->core,
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SI3054_VERB_WRITE_NODE))
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return -ENOMEM;
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snd_hda_codec_write(codec, AC_NODE_ROOT, 0, AC_VERB_SET_CODEC_RESET, 0);
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snd_hda_codec_write(codec, codec->core.mfg, 0, AC_VERB_SET_STREAM_FORMAT, 0);
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SET_REG(codec, SI3054_LINE_RATE, 9600);
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SET_REG(codec, SI3054_LINE_LEVEL, SI3054_DTAG_MASK|SI3054_ATAG_MASK);
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SET_REG(codec, SI3054_EXTENDED_MID, 0);
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wait_count = 10;
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do {
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msleep(2);
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val = GET_REG(codec, SI3054_EXTENDED_MID);
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} while ((val & SI3054_MEI_READY) != SI3054_MEI_READY && wait_count--);
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if((val&SI3054_MEI_READY) != SI3054_MEI_READY) {
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codec_err(codec, "si3054: cannot initialize. EXT MID = %04x\n", val);
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/* let's pray that this is no fatal error */
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/* return -EACCES; */
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}
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SET_REG(codec, SI3054_GPIO_POLARITY, 0xffff);
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SET_REG(codec, SI3054_GPIO_CFG, 0x0);
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SET_REG(codec, SI3054_MISC_AFE, 0);
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SET_REG(codec, SI3054_LINE_CFG1,0x200);
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if((GET_REG(codec,SI3054_LINE_STATUS) & (1<<6)) == 0) {
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codec_dbg(codec,
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"Link Frame Detect(FDT) is not ready (line status: %04x)\n",
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GET_REG(codec,SI3054_LINE_STATUS));
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}
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spec->international = GET_REG(codec, SI3054_CHIPID) & SI3054_CHIPID_INTERNATIONAL;
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return 0;
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}
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static void si3054_free(struct hda_codec *codec)
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{
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kfree(codec->spec);
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}
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/*
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*/
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static const struct hda_codec_ops si3054_patch_ops = {
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.build_controls = si3054_build_controls,
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.build_pcms = si3054_build_pcms,
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.init = si3054_init,
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.free = si3054_free,
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};
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static int patch_si3054(struct hda_codec *codec)
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{
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struct si3054_spec *spec = kzalloc(sizeof(*spec), GFP_KERNEL);
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if (spec == NULL)
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return -ENOMEM;
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codec->spec = spec;
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codec->patch_ops = si3054_patch_ops;
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return 0;
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}
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/*
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* patch entries
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*/
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static const struct hda_device_id snd_hda_id_si3054[] = {
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HDA_CODEC_ENTRY(0x163c3055, "Si3054", patch_si3054),
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HDA_CODEC_ENTRY(0x163c3155, "Si3054", patch_si3054),
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HDA_CODEC_ENTRY(0x11c13026, "Si3054", patch_si3054),
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HDA_CODEC_ENTRY(0x11c13055, "Si3054", patch_si3054),
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HDA_CODEC_ENTRY(0x11c13155, "Si3054", patch_si3054),
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HDA_CODEC_ENTRY(0x10573055, "Si3054", patch_si3054),
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HDA_CODEC_ENTRY(0x10573057, "Si3054", patch_si3054),
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HDA_CODEC_ENTRY(0x10573155, "Si3054", patch_si3054),
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/* VIA HDA on Clevo m540 */
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HDA_CODEC_ENTRY(0x11063288, "Si3054", patch_si3054),
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/* Asus A8J Modem (SM56) */
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HDA_CODEC_ENTRY(0x15433155, "Si3054", patch_si3054),
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/* LG LW20 modem */
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HDA_CODEC_ENTRY(0x18540018, "Si3054", patch_si3054),
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{}
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};
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MODULE_DEVICE_TABLE(hdaudio, snd_hda_id_si3054);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("Si3054 HD-audio modem codec");
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static struct hda_codec_driver si3054_driver = {
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.id = snd_hda_id_si3054,
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};
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module_hda_codec_driver(si3054_driver);
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