372 lines
9.2 KiB
C
372 lines
9.2 KiB
C
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/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) */
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/*
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* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef MLX5_ABI_USER_H
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#define MLX5_ABI_USER_H
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#include <linux/types.h>
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#include <linux/if_ether.h> /* For ETH_ALEN. */
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enum {
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MLX5_QP_FLAG_SIGNATURE = 1 << 0,
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MLX5_QP_FLAG_SCATTER_CQE = 1 << 1,
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MLX5_QP_FLAG_TUNNEL_OFFLOADS = 1 << 2,
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};
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enum {
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MLX5_SRQ_FLAG_SIGNATURE = 1 << 0,
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};
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enum {
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MLX5_WQ_FLAG_SIGNATURE = 1 << 0,
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};
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/* Increment this value if any changes that break userspace ABI
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* compatibility are made.
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*/
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#define MLX5_IB_UVERBS_ABI_VERSION 1
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/* Make sure that all structs defined in this file remain laid out so
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* that they pack the same way on 32-bit and 64-bit architectures (to
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* avoid incompatibility between 32-bit userspace and 64-bit kernels).
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* In particular do not use pointer types -- pass pointers in __u64
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* instead.
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*/
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struct mlx5_ib_alloc_ucontext_req {
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__u32 total_num_bfregs;
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__u32 num_low_latency_bfregs;
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};
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enum mlx5_lib_caps {
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MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
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};
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struct mlx5_ib_alloc_ucontext_req_v2 {
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__u32 total_num_bfregs;
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__u32 num_low_latency_bfregs;
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__u32 flags;
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__u32 comp_mask;
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__u8 max_cqe_version;
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__u8 reserved0;
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__u16 reserved1;
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__u32 reserved2;
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__u64 lib_caps;
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};
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enum mlx5_ib_alloc_ucontext_resp_mask {
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MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
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};
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enum mlx5_user_cmds_supp_uhw {
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MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE = 1 << 0,
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MLX5_USER_CMDS_SUPP_UHW_CREATE_AH = 1 << 1,
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};
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/* The eth_min_inline response value is set to off-by-one vs the FW
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* returned value to allow user-space to deal with older kernels.
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*/
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enum mlx5_user_inline_mode {
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MLX5_USER_INLINE_MODE_NA,
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MLX5_USER_INLINE_MODE_NONE,
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MLX5_USER_INLINE_MODE_L2,
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MLX5_USER_INLINE_MODE_IP,
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MLX5_USER_INLINE_MODE_TCP_UDP,
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};
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struct mlx5_ib_alloc_ucontext_resp {
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__u32 qp_tab_size;
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__u32 bf_reg_size;
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__u32 tot_bfregs;
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__u32 cache_line_size;
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__u16 max_sq_desc_sz;
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__u16 max_rq_desc_sz;
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__u32 max_send_wqebb;
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__u32 max_recv_wr;
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__u32 max_srq_recv_wr;
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__u16 num_ports;
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__u16 reserved1;
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__u32 comp_mask;
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__u32 response_length;
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__u8 cqe_version;
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__u8 cmds_supp_uhw;
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__u8 eth_min_inline;
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__u8 reserved2;
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__u64 hca_core_clock_offset;
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__u32 log_uar_size;
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__u32 num_uars_per_page;
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};
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struct mlx5_ib_alloc_pd_resp {
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__u32 pdn;
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};
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struct mlx5_ib_tso_caps {
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__u32 max_tso; /* Maximum tso payload size in bytes */
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/* Corresponding bit will be set if qp type from
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* 'enum ib_qp_type' is supported, e.g.
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* supported_qpts |= 1 << IB_QPT_UD
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*/
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__u32 supported_qpts;
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};
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struct mlx5_ib_rss_caps {
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__u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
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__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
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__u8 reserved[7];
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};
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enum mlx5_ib_cqe_comp_res_format {
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MLX5_IB_CQE_RES_FORMAT_HASH = 1 << 0,
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MLX5_IB_CQE_RES_FORMAT_CSUM = 1 << 1,
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MLX5_IB_CQE_RES_RESERVED = 1 << 2,
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};
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struct mlx5_ib_cqe_comp_caps {
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__u32 max_num;
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__u32 supported_format; /* enum mlx5_ib_cqe_comp_res_format */
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};
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struct mlx5_packet_pacing_caps {
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__u32 qp_rate_limit_min;
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__u32 qp_rate_limit_max; /* In kpbs */
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/* Corresponding bit will be set if qp type from
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* 'enum ib_qp_type' is supported, e.g.
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* supported_qpts |= 1 << IB_QPT_RAW_PACKET
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*/
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__u32 supported_qpts;
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__u32 reserved;
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};
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enum mlx5_ib_mpw_caps {
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MPW_RESERVED = 1 << 0,
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MLX5_IB_ALLOW_MPW = 1 << 1,
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MLX5_IB_SUPPORT_EMPW = 1 << 2,
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};
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enum mlx5_ib_sw_parsing_offloads {
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MLX5_IB_SW_PARSING = 1 << 0,
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MLX5_IB_SW_PARSING_CSUM = 1 << 1,
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MLX5_IB_SW_PARSING_LSO = 1 << 2,
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};
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struct mlx5_ib_sw_parsing_caps {
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__u32 sw_parsing_offloads; /* enum mlx5_ib_sw_parsing_offloads */
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/* Corresponding bit will be set if qp type from
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* 'enum ib_qp_type' is supported, e.g.
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* supported_qpts |= 1 << IB_QPT_RAW_PACKET
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*/
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__u32 supported_qpts;
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};
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struct mlx5_ib_striding_rq_caps {
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__u32 min_single_stride_log_num_of_bytes;
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__u32 max_single_stride_log_num_of_bytes;
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__u32 min_single_wqe_log_num_of_strides;
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__u32 max_single_wqe_log_num_of_strides;
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/* Corresponding bit will be set if qp type from
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* 'enum ib_qp_type' is supported, e.g.
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* supported_qpts |= 1 << IB_QPT_RAW_PACKET
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*/
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__u32 supported_qpts;
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__u32 reserved;
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};
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enum mlx5_ib_query_dev_resp_flags {
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/* Support 128B CQE compression */
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MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP = 1 << 0,
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MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD = 1 << 1,
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};
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enum mlx5_ib_tunnel_offloads {
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MLX5_IB_TUNNELED_OFFLOADS_VXLAN = 1 << 0,
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MLX5_IB_TUNNELED_OFFLOADS_GRE = 1 << 1,
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MLX5_IB_TUNNELED_OFFLOADS_GENEVE = 1 << 2
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};
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struct mlx5_ib_query_device_resp {
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__u32 comp_mask;
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__u32 response_length;
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struct mlx5_ib_tso_caps tso_caps;
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struct mlx5_ib_rss_caps rss_caps;
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struct mlx5_ib_cqe_comp_caps cqe_comp_caps;
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struct mlx5_packet_pacing_caps packet_pacing_caps;
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__u32 mlx5_ib_support_multi_pkt_send_wqes;
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__u32 flags; /* Use enum mlx5_ib_query_dev_resp_flags */
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struct mlx5_ib_sw_parsing_caps sw_parsing_caps;
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struct mlx5_ib_striding_rq_caps striding_rq_caps;
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__u32 tunnel_offloads_caps; /* enum mlx5_ib_tunnel_offloads */
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__u32 reserved;
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};
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enum mlx5_ib_create_cq_flags {
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MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD = 1 << 0,
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};
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struct mlx5_ib_create_cq {
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__u64 buf_addr;
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__u64 db_addr;
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__u32 cqe_size;
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__u8 cqe_comp_en;
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__u8 cqe_comp_res_format;
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__u16 flags;
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};
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struct mlx5_ib_create_cq_resp {
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__u32 cqn;
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__u32 reserved;
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};
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struct mlx5_ib_resize_cq {
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__u64 buf_addr;
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__u16 cqe_size;
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__u16 reserved0;
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__u32 reserved1;
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};
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struct mlx5_ib_create_srq {
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__u64 buf_addr;
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__u64 db_addr;
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__u32 flags;
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__u32 reserved0; /* explicit padding (optional on i386) */
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__u32 uidx;
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__u32 reserved1;
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};
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struct mlx5_ib_create_srq_resp {
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__u32 srqn;
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__u32 reserved;
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};
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struct mlx5_ib_create_qp {
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__u64 buf_addr;
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__u64 db_addr;
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__u32 sq_wqe_count;
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__u32 rq_wqe_count;
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__u32 rq_wqe_shift;
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__u32 flags;
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__u32 uidx;
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__u32 reserved0;
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__u64 sq_buf_addr;
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};
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/* RX Hash function flags */
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enum mlx5_rx_hash_function_flags {
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MLX5_RX_HASH_FUNC_TOEPLITZ = 1 << 0,
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};
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/*
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* RX Hash flags, these flags allows to set which incoming packet's field should
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* participates in RX Hash. Each flag represent certain packet's field,
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* when the flag is set the field that is represented by the flag will
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* participate in RX Hash calculation.
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* Note: *IPV4 and *IPV6 flags can't be enabled together on the same QP
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* and *TCP and *UDP flags can't be enabled together on the same QP.
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*/
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enum mlx5_rx_hash_fields {
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MLX5_RX_HASH_SRC_IPV4 = 1 << 0,
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MLX5_RX_HASH_DST_IPV4 = 1 << 1,
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MLX5_RX_HASH_SRC_IPV6 = 1 << 2,
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MLX5_RX_HASH_DST_IPV6 = 1 << 3,
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MLX5_RX_HASH_SRC_PORT_TCP = 1 << 4,
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MLX5_RX_HASH_DST_PORT_TCP = 1 << 5,
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MLX5_RX_HASH_SRC_PORT_UDP = 1 << 6,
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MLX5_RX_HASH_DST_PORT_UDP = 1 << 7,
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/* Save bits for future fields */
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MLX5_RX_HASH_INNER = 1 << 31
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};
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struct mlx5_ib_create_qp_rss {
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__u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
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__u8 rx_hash_function; /* enum mlx5_rx_hash_function_flags */
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__u8 rx_key_len; /* valid only for Toeplitz */
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__u8 reserved[6];
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__u8 rx_hash_key[128]; /* valid only for Toeplitz */
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__u32 comp_mask;
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__u32 flags;
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};
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struct mlx5_ib_create_qp_resp {
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__u32 bfreg_index;
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};
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struct mlx5_ib_alloc_mw {
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__u32 comp_mask;
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__u8 num_klms;
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__u8 reserved1;
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__u16 reserved2;
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};
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enum mlx5_ib_create_wq_mask {
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MLX5_IB_CREATE_WQ_STRIDING_RQ = (1 << 0),
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};
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struct mlx5_ib_create_wq {
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__u64 buf_addr;
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__u64 db_addr;
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__u32 rq_wqe_count;
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__u32 rq_wqe_shift;
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__u32 user_index;
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__u32 flags;
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__u32 comp_mask;
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__u32 single_stride_log_num_of_bytes;
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__u32 single_wqe_log_num_of_strides;
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__u32 two_byte_shift_en;
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};
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struct mlx5_ib_create_ah_resp {
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__u32 response_length;
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__u8 dmac[ETH_ALEN];
|
||
|
|
__u8 reserved[6];
|
||
|
|
};
|
||
|
|
|
||
|
|
struct mlx5_ib_create_wq_resp {
|
||
|
|
__u32 response_length;
|
||
|
|
__u32 reserved;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct mlx5_ib_create_rwq_ind_tbl_resp {
|
||
|
|
__u32 response_length;
|
||
|
|
__u32 reserved;
|
||
|
|
};
|
||
|
|
|
||
|
|
struct mlx5_ib_modify_wq {
|
||
|
|
__u32 comp_mask;
|
||
|
|
__u32 reserved;
|
||
|
|
};
|
||
|
|
#endif /* MLX5_ABI_USER_H */
|