310 lines
8.9 KiB
C
310 lines
8.9 KiB
C
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/**************************************************************************
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Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
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All Rights Reserved.
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the
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"Software"), to deal in the Software without restriction, including
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without limitation the rights to use, copy, modify, merge, publish,
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distribute, sub license, and/or sell copies of the Software, and to
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permit persons to whom the Software is furnished to do so, subject to
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the following conditions:
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The above copyright notice and this permission notice (including the
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next paragraph) shall be included in all copies or substantial portions
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of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
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ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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**************************************************************************/
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/*
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* Authors:
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* Kevin E. Martin <kevin@precisioninsight.com>
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*/
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/* I/O register offsets */
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#define SRX VGA_SEQ_I
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#define GRX VGA_GFX_I
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#define ARX VGA_ATT_IW
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#define XRX 0x3D6
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#define MRX 0x3D2
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/* VGA Color Palette Registers */
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#define DACMASK 0x3C6
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#define DACSTATE 0x3C7
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#define DACRX 0x3C7
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#define DACWX 0x3C8
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#define DACDATA 0x3C9
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/* CRT Controller Registers (CRX) */
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#define START_ADDR_HI 0x0C
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#define START_ADDR_LO 0x0D
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#define VERT_SYNC_END 0x11
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#define EXT_VERT_TOTAL 0x30
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#define EXT_VERT_DISPLAY 0x31
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#define EXT_VERT_SYNC_START 0x32
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#define EXT_VERT_BLANK_START 0x33
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#define EXT_HORIZ_TOTAL 0x35
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#define EXT_HORIZ_BLANK 0x39
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#define EXT_START_ADDR 0x40
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#define EXT_START_ADDR_ENABLE 0x80
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#define EXT_OFFSET 0x41
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#define EXT_START_ADDR_HI 0x42
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#define INTERLACE_CNTL 0x70
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#define INTERLACE_ENABLE 0x80
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#define INTERLACE_DISABLE 0x00
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/* Miscellaneous Output Register */
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#define MSR_R 0x3CC
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#define MSR_W 0x3C2
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#define IO_ADDR_SELECT 0x01
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#define MDA_BASE 0x3B0
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#define CGA_BASE 0x3D0
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/* System Configuration Extension Registers (XRX) */
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#define IO_CTNL 0x09
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#define EXTENDED_ATTR_CNTL 0x02
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#define EXTENDED_CRTC_CNTL 0x01
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#define ADDRESS_MAPPING 0x0A
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#define PACKED_MODE_ENABLE 0x04
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#define LINEAR_MODE_ENABLE 0x02
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#define PAGE_MAPPING_ENABLE 0x01
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#define BITBLT_CNTL 0x20
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#define COLEXP_MODE 0x30
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#define COLEXP_8BPP 0x00
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#define COLEXP_16BPP 0x10
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#define COLEXP_24BPP 0x20
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#define COLEXP_RESERVED 0x30
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#define CHIP_RESET 0x02
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#define BITBLT_STATUS 0x01
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#define DISPLAY_CNTL 0x40
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#define VGA_WRAP_MODE 0x02
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#define VGA_WRAP_AT_256KB 0x00
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#define VGA_NO_WRAP 0x02
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#define GUI_MODE 0x01
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#define STANDARD_VGA_MODE 0x00
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#define HIRES_MODE 0x01
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#define DRAM_ROW_TYPE 0x50
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#define DRAM_ROW_0 0x07
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#define DRAM_ROW_0_SDRAM 0x00
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#define DRAM_ROW_0_EMPTY 0x07
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#define DRAM_ROW_1 0x38
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#define DRAM_ROW_1_SDRAM 0x00
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#define DRAM_ROW_1_EMPTY 0x38
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#define DRAM_ROW_CNTL_LO 0x51
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#define DRAM_CAS_LATENCY 0x10
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#define DRAM_RAS_TIMING 0x08
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#define DRAM_RAS_PRECHARGE 0x04
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#define DRAM_ROW_CNTL_HI 0x52
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#define DRAM_EXT_CNTL 0x53
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#define DRAM_REFRESH_RATE 0x03
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#define DRAM_REFRESH_DISABLE 0x00
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#define DRAM_REFRESH_60HZ 0x01
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#define DRAM_REFRESH_FAST_TEST 0x02
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#define DRAM_REFRESH_RESERVED 0x03
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#define DRAM_TIMING 0x54
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#define DRAM_ROW_BNDRY_0 0x55
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#define DRAM_ROW_BNDRY_1 0x56
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#define DPMS_SYNC_SELECT 0x61
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#define VSYNC_CNTL 0x08
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#define VSYNC_ON 0x00
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#define VSYNC_OFF 0x08
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#define HSYNC_CNTL 0x02
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#define HSYNC_ON 0x00
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#define HSYNC_OFF 0x02
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#define PIXPIPE_CONFIG_0 0x80
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#define DAC_8_BIT 0x80
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#define DAC_6_BIT 0x00
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#define HW_CURSOR_ENABLE 0x10
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#define EXTENDED_PALETTE 0x01
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#define PIXPIPE_CONFIG_1 0x81
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#define DISPLAY_COLOR_MODE 0x0F
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#define DISPLAY_VGA_MODE 0x00
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#define DISPLAY_8BPP_MODE 0x02
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#define DISPLAY_15BPP_MODE 0x04
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#define DISPLAY_16BPP_MODE 0x05
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#define DISPLAY_24BPP_MODE 0x06
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#define DISPLAY_32BPP_MODE 0x07
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#define PIXPIPE_CONFIG_2 0x82
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#define DISPLAY_GAMMA_ENABLE 0x08
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#define DISPLAY_GAMMA_DISABLE 0x00
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#define OVERLAY_GAMMA_ENABLE 0x04
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#define OVERLAY_GAMMA_DISABLE 0x00
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#define CURSOR_CONTROL 0xA0
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#define CURSOR_ORIGIN_SCREEN 0x00
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#define CURSOR_ORIGIN_DISPLAY 0x10
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#define CURSOR_MODE 0x07
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#define CURSOR_MODE_DISABLE 0x00
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#define CURSOR_MODE_32_4C_AX 0x01
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#define CURSOR_MODE_128_2C 0x02
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#define CURSOR_MODE_128_1C 0x03
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#define CURSOR_MODE_64_3C 0x04
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#define CURSOR_MODE_64_4C_AX 0x05
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#define CURSOR_MODE_64_4C 0x06
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#define CURSOR_MODE_RESERVED 0x07
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#define CURSOR_BASEADDR_LO 0xA2
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#define CURSOR_BASEADDR_HI 0xA3
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#define CURSOR_X_LO 0xA4
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#define CURSOR_X_HI 0xA5
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#define CURSOR_X_POS 0x00
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#define CURSOR_X_NEG 0x80
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#define CURSOR_Y_LO 0xA6
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#define CURSOR_Y_HI 0xA7
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#define CURSOR_Y_POS 0x00
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#define CURSOR_Y_NEG 0x80
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#define VCLK2_VCO_M 0xC8
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#define VCLK2_VCO_N 0xC9
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#define VCLK2_VCO_MN_MSBS 0xCA
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#define VCO_N_MSBS 0x30
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#define VCO_M_MSBS 0x03
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#define VCLK2_VCO_DIV_SEL 0xCB
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#define POST_DIV_SELECT 0x70
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#define POST_DIV_1 0x00
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#define POST_DIV_2 0x10
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#define POST_DIV_4 0x20
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#define POST_DIV_8 0x30
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#define POST_DIV_16 0x40
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#define POST_DIV_32 0x50
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#define VCO_LOOP_DIV_BY_4M 0x00
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#define VCO_LOOP_DIV_BY_16M 0x04
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#define REF_CLK_DIV_BY_5 0x02
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#define REF_DIV_4 0x00
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#define REF_DIV_1 0x01
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#define PLL_CNTL 0xCE
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#define PLL_MEMCLK_SEL 0x03
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#define PLL_MEMCLK__66667KHZ 0x00
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#define PLL_MEMCLK__75000KHZ 0x01
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#define PLL_MEMCLK__88889KHZ 0x02
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#define PLL_MEMCLK_100000KHZ 0x03
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/* Multimedia Extension Registers (MRX) */
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#define ACQ_CNTL_1 0x02
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#define ACQ_CNTL_2 0x03
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#define FRAME_CAP_MODE 0x01
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#define CONT_CAP_MODE 0x00
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#define SINGLE_CAP_MODE 0x01
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#define ACQ_CNTL_3 0x04
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#define COL_KEY_CNTL_1 0x3C
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#define BLANK_DISP_OVERLAY 0x20
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/* FIFOs */
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#define LP_FIFO 0x1000
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#define HP_FIFO 0x2000
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#define INSTPNT 0x3040
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#define LP_FIFO_COUNT 0x3040
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#define HP_FIFO_COUNT 0x3041
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/* FIFO Commands */
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#define CLIENT 0xE0000000
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#define CLIENT_2D 0x60000000
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/* Command Parser Mode Register */
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#define COMPARS 0x3038
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#define TWO_D_INST_DISABLE 0x08
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#define THREE_D_INST_DISABLE 0x04
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#define STATE_VAR_UPDATE_DISABLE 0x02
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#define PAL_STIP_DISABLE 0x01
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/* Interrupt Control Registers */
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#define IER 0x3030
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#define IIR 0x3032
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#define IMR 0x3034
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#define ISR 0x3036
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#define VMIINTB_EVENT 0x2000
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#define GPIO4_INT 0x1000
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#define DISP_FLIP_EVENT 0x0800
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#define DVD_PORT_DMA 0x0400
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#define DISP_VBLANK 0x0200
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#define FIFO_EMPTY_DMA_DONE 0x0100
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#define INST_PARSER_ERROR 0x0080
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#define USER_DEFINED 0x0040
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#define BREAKPOINT 0x0020
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#define DISP_HORIZ_COUNT 0x0010
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#define DISP_VSYNC 0x0008
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#define CAPTURE_HORIZ_COUNT 0x0004
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#define CAPTURE_VSYNC 0x0002
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#define THREE_D_PIPE_FLUSHED 0x0001
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/* FIFO Watermark and Burst Length Control Register */
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#define FWATER_BLC 0x00006000
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#define LMI_BURST_LENGTH 0x7F000000
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#define LMI_FIFO_WATERMARK 0x003F0000
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#define AGP_BURST_LENGTH 0x00007F00
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#define AGP_FIFO_WATERMARK 0x0000003F
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/* BitBLT Registers */
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#define SRC_DST_PITCH 0x00040000
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#define DST_PITCH 0x1FFF0000
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#define SRC_PITCH 0x00001FFF
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#define COLEXP_BG_COLOR 0x00040004
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#define COLEXP_FG_COLOR 0x00040008
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#define MONO_SRC_CNTL 0x0004000C
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#define MONO_USE_COLEXP 0x00000000
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#define MONO_USE_SRCEXP 0x08000000
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#define MONO_DATA_ALIGN 0x07000000
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#define MONO_BIT_ALIGN 0x01000000
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#define MONO_BYTE_ALIGN 0x02000000
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#define MONO_WORD_ALIGN 0x03000000
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#define MONO_DWORD_ALIGN 0x04000000
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#define MONO_QWORD_ALIGN 0x05000000
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#define MONO_SRC_INIT_DSCRD 0x003F0000
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#define MONO_SRC_RIGHT_CLIP 0x00003F00
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#define MONO_SRC_LEFT_CLIP 0x0000003F
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#define BITBLT_CONTROL 0x00040010
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#define BLTR_STATUS 0x80000000
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#define DYN_DEPTH 0x03000000
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#define DYN_DEPTH_8BPP 0x00000000
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#define DYN_DEPTH_16BPP 0x01000000
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#define DYN_DEPTH_24BPP 0x02000000
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#define DYN_DEPTH_32BPP 0x03000000 /* Unimplemented on the i740 */
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#define DYN_DEPTH_ENABLE 0x00800000
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#define PAT_VERT_ALIGN 0x00700000
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#define SOLID_PAT_SELECT 0x00080000
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#define PAT_IS_IN_COLOR 0x00000000
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#define PAT_IS_MONO 0x00040000
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#define MONO_PAT_TRANSP 0x00020000
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#define COLOR_TRANSP_ROP 0x00000000
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#define COLOR_TRANSP_DST 0x00008000
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#define COLOR_TRANSP_EQ 0x00000000
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#define COLOR_TRANSP_NOT_EQ 0x00010000
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#define COLOR_TRANSP_ENABLE 0x00004000
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#define MONO_SRC_TRANSP 0x00002000
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#define SRC_IS_IN_COLOR 0x00000000
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#define SRC_IS_MONO 0x00001000
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#define SRC_USE_SRC_ADDR 0x00000000
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#define SRC_USE_BLTDATA 0x00000400
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#define BLT_TOP_TO_BOT 0x00000000
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#define BLT_BOT_TO_TOP 0x00000200
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#define BLT_LEFT_TO_RIGHT 0x00000000
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#define BLT_RIGHT_TO_LEFT 0x00000100
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#define BLT_ROP 0x000000FF
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#define BLT_PAT_ADDR 0x00040014
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#define BLT_SRC_ADDR 0x00040018
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#define BLT_DST_ADDR 0x0004001C
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#define BLT_DST_H_W 0x00040020
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#define BLT_DST_HEIGHT 0x1FFF0000
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#define BLT_DST_WIDTH 0x00001FFF
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#define SRCEXP_BG_COLOR 0x00040024
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#define SRCEXP_FG_COLOR 0x00040028
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#define BLTDATA 0x00050000
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