297 lines
8.3 KiB
C
297 lines
8.3 KiB
C
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// SPDX-License-Identifier: GPL-2.0
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/*
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* xHCI host controller driver
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*
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* Copyright (C) 2008 Intel Corp.
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*
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* Author: Sarah Sharp
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* Some code borrowed from the Linux EHCI driver.
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*/
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#include "xhci.h"
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#define XHCI_INIT_VALUE 0x0
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/* Add verbose debugging later, just print everything for now */
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void xhci_dbg_regs(struct xhci_hcd *xhci)
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{
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u32 temp;
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xhci_dbg(xhci, "// xHCI capability registers at %p:\n",
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xhci->cap_regs);
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temp = readl(&xhci->cap_regs->hc_capbase);
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xhci_dbg(xhci, "// @%p = 0x%x (CAPLENGTH AND HCIVERSION)\n",
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&xhci->cap_regs->hc_capbase, temp);
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xhci_dbg(xhci, "// CAPLENGTH: 0x%x\n",
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(unsigned int) HC_LENGTH(temp));
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xhci_dbg(xhci, "// HCIVERSION: 0x%x\n",
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(unsigned int) HC_VERSION(temp));
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xhci_dbg(xhci, "// xHCI operational registers at %p:\n", xhci->op_regs);
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temp = readl(&xhci->cap_regs->run_regs_off);
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xhci_dbg(xhci, "// @%p = 0x%x RTSOFF\n",
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&xhci->cap_regs->run_regs_off,
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(unsigned int) temp & RTSOFF_MASK);
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xhci_dbg(xhci, "// xHCI runtime registers at %p:\n", xhci->run_regs);
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temp = readl(&xhci->cap_regs->db_off);
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xhci_dbg(xhci, "// @%p = 0x%x DBOFF\n", &xhci->cap_regs->db_off, temp);
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xhci_dbg(xhci, "// Doorbell array at %p:\n", xhci->dba);
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}
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static void xhci_print_cap_regs(struct xhci_hcd *xhci)
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{
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u32 temp;
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u32 hci_version;
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xhci_dbg(xhci, "xHCI capability registers at %p:\n", xhci->cap_regs);
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temp = readl(&xhci->cap_regs->hc_capbase);
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hci_version = HC_VERSION(temp);
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xhci_dbg(xhci, "CAPLENGTH AND HCIVERSION 0x%x:\n",
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(unsigned int) temp);
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xhci_dbg(xhci, "CAPLENGTH: 0x%x\n",
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(unsigned int) HC_LENGTH(temp));
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xhci_dbg(xhci, "HCIVERSION: 0x%x\n", hci_version);
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temp = readl(&xhci->cap_regs->hcs_params1);
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xhci_dbg(xhci, "HCSPARAMS 1: 0x%x\n",
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(unsigned int) temp);
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xhci_dbg(xhci, " Max device slots: %u\n",
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(unsigned int) HCS_MAX_SLOTS(temp));
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xhci_dbg(xhci, " Max interrupters: %u\n",
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(unsigned int) HCS_MAX_INTRS(temp));
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xhci_dbg(xhci, " Max ports: %u\n",
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(unsigned int) HCS_MAX_PORTS(temp));
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temp = readl(&xhci->cap_regs->hcs_params2);
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xhci_dbg(xhci, "HCSPARAMS 2: 0x%x\n",
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(unsigned int) temp);
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xhci_dbg(xhci, " Isoc scheduling threshold: %u\n",
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(unsigned int) HCS_IST(temp));
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xhci_dbg(xhci, " Maximum allowed segments in event ring: %u\n",
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(unsigned int) HCS_ERST_MAX(temp));
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temp = readl(&xhci->cap_regs->hcs_params3);
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xhci_dbg(xhci, "HCSPARAMS 3 0x%x:\n",
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(unsigned int) temp);
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xhci_dbg(xhci, " Worst case U1 device exit latency: %u\n",
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(unsigned int) HCS_U1_LATENCY(temp));
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xhci_dbg(xhci, " Worst case U2 device exit latency: %u\n",
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(unsigned int) HCS_U2_LATENCY(temp));
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temp = readl(&xhci->cap_regs->hcc_params);
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xhci_dbg(xhci, "HCC PARAMS 0x%x:\n", (unsigned int) temp);
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xhci_dbg(xhci, " HC generates %s bit addresses\n",
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HCC_64BIT_ADDR(temp) ? "64" : "32");
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xhci_dbg(xhci, " HC %s Contiguous Frame ID Capability\n",
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HCC_CFC(temp) ? "has" : "hasn't");
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xhci_dbg(xhci, " HC %s generate Stopped - Short Package event\n",
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HCC_SPC(temp) ? "can" : "can't");
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/* FIXME */
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xhci_dbg(xhci, " FIXME: more HCCPARAMS debugging\n");
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temp = readl(&xhci->cap_regs->run_regs_off);
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xhci_dbg(xhci, "RTSOFF 0x%x:\n", temp & RTSOFF_MASK);
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/* xhci 1.1 controllers have the HCCPARAMS2 register */
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if (hci_version > 0x100) {
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temp = readl(&xhci->cap_regs->hcc_params2);
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xhci_dbg(xhci, "HCC PARAMS2 0x%x:\n", (unsigned int) temp);
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xhci_dbg(xhci, " HC %s Force save context capability",
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HCC2_FSC(temp) ? "supports" : "doesn't support");
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xhci_dbg(xhci, " HC %s Large ESIT Payload Capability",
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HCC2_LEC(temp) ? "supports" : "doesn't support");
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xhci_dbg(xhci, " HC %s Extended TBC capability",
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HCC2_ETC(temp) ? "supports" : "doesn't support");
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}
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}
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static void xhci_print_command_reg(struct xhci_hcd *xhci)
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{
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u32 temp;
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temp = readl(&xhci->op_regs->command);
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xhci_dbg(xhci, "USBCMD 0x%x:\n", temp);
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xhci_dbg(xhci, " HC is %s\n",
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(temp & CMD_RUN) ? "running" : "being stopped");
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xhci_dbg(xhci, " HC has %sfinished hard reset\n",
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(temp & CMD_RESET) ? "not " : "");
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xhci_dbg(xhci, " Event Interrupts %s\n",
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(temp & CMD_EIE) ? "enabled " : "disabled");
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xhci_dbg(xhci, " Host System Error Interrupts %s\n",
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(temp & CMD_HSEIE) ? "enabled " : "disabled");
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xhci_dbg(xhci, " HC has %sfinished light reset\n",
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(temp & CMD_LRESET) ? "not " : "");
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}
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static void xhci_print_status(struct xhci_hcd *xhci)
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{
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u32 temp;
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temp = readl(&xhci->op_regs->status);
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xhci_dbg(xhci, "USBSTS 0x%x:\n", temp);
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xhci_dbg(xhci, " Event ring is %sempty\n",
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(temp & STS_EINT) ? "not " : "");
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xhci_dbg(xhci, " %sHost System Error\n",
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(temp & STS_FATAL) ? "WARNING: " : "No ");
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xhci_dbg(xhci, " HC is %s\n",
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(temp & STS_HALT) ? "halted" : "running");
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}
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static void xhci_print_op_regs(struct xhci_hcd *xhci)
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{
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xhci_dbg(xhci, "xHCI operational registers at %p:\n", xhci->op_regs);
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xhci_print_command_reg(xhci);
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xhci_print_status(xhci);
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}
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static void xhci_print_ports(struct xhci_hcd *xhci)
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{
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__le32 __iomem *addr;
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int i, j;
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int ports;
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char *names[NUM_PORT_REGS] = {
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"status",
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"power",
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"link",
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"reserved",
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};
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ports = HCS_MAX_PORTS(xhci->hcs_params1);
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addr = &xhci->op_regs->port_status_base;
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for (i = 0; i < ports; i++) {
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for (j = 0; j < NUM_PORT_REGS; j++) {
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xhci_dbg(xhci, "%p port %s reg = 0x%x\n",
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addr, names[j],
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(unsigned int) readl(addr));
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addr++;
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}
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}
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}
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void xhci_print_ir_set(struct xhci_hcd *xhci, int set_num)
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{
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struct xhci_intr_reg __iomem *ir_set = &xhci->run_regs->ir_set[set_num];
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void __iomem *addr;
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u32 temp;
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u64 temp_64;
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addr = &ir_set->irq_pending;
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temp = readl(addr);
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if (temp == XHCI_INIT_VALUE)
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return;
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xhci_dbg(xhci, " %p: ir_set[%i]\n", ir_set, set_num);
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xhci_dbg(xhci, " %p: ir_set.pending = 0x%x\n", addr,
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(unsigned int)temp);
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addr = &ir_set->irq_control;
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temp = readl(addr);
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xhci_dbg(xhci, " %p: ir_set.control = 0x%x\n", addr,
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(unsigned int)temp);
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addr = &ir_set->erst_size;
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temp = readl(addr);
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xhci_dbg(xhci, " %p: ir_set.erst_size = 0x%x\n", addr,
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(unsigned int)temp);
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addr = &ir_set->rsvd;
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temp = readl(addr);
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if (temp != XHCI_INIT_VALUE)
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xhci_dbg(xhci, " WARN: %p: ir_set.rsvd = 0x%x\n",
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addr, (unsigned int)temp);
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addr = &ir_set->erst_base;
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temp_64 = xhci_read_64(xhci, addr);
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xhci_dbg(xhci, " %p: ir_set.erst_base = @%08llx\n",
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addr, temp_64);
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addr = &ir_set->erst_dequeue;
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temp_64 = xhci_read_64(xhci, addr);
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xhci_dbg(xhci, " %p: ir_set.erst_dequeue = @%08llx\n",
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addr, temp_64);
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}
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void xhci_print_run_regs(struct xhci_hcd *xhci)
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{
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u32 temp;
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int i;
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xhci_dbg(xhci, "xHCI runtime registers at %p:\n", xhci->run_regs);
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temp = readl(&xhci->run_regs->microframe_index);
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xhci_dbg(xhci, " %p: Microframe index = 0x%x\n",
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&xhci->run_regs->microframe_index,
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(unsigned int) temp);
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for (i = 0; i < 7; i++) {
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temp = readl(&xhci->run_regs->rsvd[i]);
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if (temp != XHCI_INIT_VALUE)
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xhci_dbg(xhci, " WARN: %p: Rsvd[%i] = 0x%x\n",
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&xhci->run_regs->rsvd[i],
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i, (unsigned int) temp);
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}
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}
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void xhci_print_registers(struct xhci_hcd *xhci)
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{
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xhci_print_cap_regs(xhci);
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xhci_print_op_regs(xhci);
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xhci_print_ports(xhci);
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}
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void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
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{
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u64 addr = erst->erst_dma_addr;
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int i;
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struct xhci_erst_entry *entry;
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for (i = 0; i < erst->num_entries; i++) {
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entry = &erst->entries[i];
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xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n",
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addr,
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lower_32_bits(le64_to_cpu(entry->seg_addr)),
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upper_32_bits(le64_to_cpu(entry->seg_addr)),
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le32_to_cpu(entry->seg_size),
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le32_to_cpu(entry->rsvd));
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addr += sizeof(*entry);
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}
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}
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void xhci_dbg_cmd_ptrs(struct xhci_hcd *xhci)
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{
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u64 val;
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val = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
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xhci_dbg(xhci, "// xHC command ring deq ptr low bits + flags = @%08x\n",
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lower_32_bits(val));
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xhci_dbg(xhci, "// xHC command ring deq ptr high bits = @%08x\n",
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upper_32_bits(val));
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}
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char *xhci_get_slot_state(struct xhci_hcd *xhci,
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struct xhci_container_ctx *ctx)
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{
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struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
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int state = GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state));
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return xhci_slot_state_string(state);
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}
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void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
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const char *fmt, ...)
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{
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struct va_format vaf;
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va_list args;
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va_start(args, fmt);
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vaf.fmt = fmt;
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vaf.va = &args;
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xhci_dbg(xhci, "%pV\n", &vaf);
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trace(&vaf);
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va_end(args);
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}
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EXPORT_SYMBOL_GPL(xhci_dbg_trace);
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