490 lines
12 KiB
C
490 lines
12 KiB
C
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* bdc.h - header for the BRCM BDC USB3.0 device controller
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*
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* Copyright (C) 2014 Broadcom Corporation
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*
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* Author: Ashwini Pahuja
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*/
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#ifndef __LINUX_BDC_H__
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#define __LINUX_BDC_H__
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#include <linux/kernel.h>
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#include <linux/usb.h>
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#include <linux/device.h>
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#include <linux/spinlock.h>
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#include <linux/list.h>
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#include <linux/dma-mapping.h>
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#include <linux/mm.h>
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#include <linux/debugfs.h>
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#include <linux/usb/ch9.h>
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#include <linux/usb/gadget.h>
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#include <asm/unaligned.h>
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#define BRCM_BDC_NAME "bdc"
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#define BRCM_BDC_DESC "Broadcom USB Device Controller driver"
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#define DMA_ADDR_INVALID (~(dma_addr_t)0)
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/* BDC command operation timeout in usec*/
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#define BDC_CMD_TIMEOUT 1000
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/* BDC controller operation timeout in usec*/
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#define BDC_COP_TIMEOUT 500
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/*
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* Maximum size of ep0 response buffer for ch9 requests,
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* the set_sel request uses 6 so far, the max.
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*/
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#define EP0_RESPONSE_BUFF 6
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/* Start with SS as default */
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#define EP0_MAX_PKT_SIZE 512
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/* 64 entries in a SRR */
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#define NUM_SR_ENTRIES 64
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/* Num of bds per table */
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#define NUM_BDS_PER_TABLE 32
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/* Num of tables in bd list for control,bulk and Int ep */
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#define NUM_TABLES 2
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/* Num of tables in bd list for Isoch ep */
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#define NUM_TABLES_ISOCH 6
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/* U1 Timeout default: 248usec */
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#define U1_TIMEOUT 0xf8
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/* Interrupt coalescence in usec */
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#define INT_CLS 500
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/* Register offsets */
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/* Configuration and Capability registers */
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#define BDC_BDCCFG0 0x00
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#define BDC_BDCCFG1 0x04
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#define BDC_BDCCAP0 0x08
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#define BDC_BDCCAP1 0x0c
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#define BDC_CMDPAR0 0x10
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#define BDC_CMDPAR1 0x14
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#define BDC_CMDPAR2 0x18
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#define BDC_CMDSC 0x1c
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#define BDC_USPC 0x20
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#define BDC_USPPMS 0x28
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#define BDC_USPPM2 0x2c
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#define BDC_SPBBAL 0x38
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#define BDC_SPBBAH 0x3c
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#define BDC_BDCSC 0x40
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#define BDC_XSFNTF 0x4c
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#define BDC_DVCSA 0x50
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#define BDC_DVCSB 0x54
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#define BDC_EPSTS0 0x60
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#define BDC_EPSTS1 0x64
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#define BDC_EPSTS2 0x68
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#define BDC_EPSTS3 0x6c
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#define BDC_EPSTS4 0x70
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#define BDC_EPSTS5 0x74
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#define BDC_EPSTS6 0x78
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#define BDC_EPSTS7 0x7c
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#define BDC_SRRBAL(n) (0x200 + (n * 0x10))
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#define BDC_SRRBAH(n) (0x204 + (n * 0x10))
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#define BDC_SRRINT(n) (0x208 + (n * 0x10))
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#define BDC_INTCTLS(n) (0x20c + (n * 0x10))
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/* Extended capability regs */
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#define BDC_FSCNOC 0xcd4
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#define BDC_FSCNIC 0xce4
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#define NUM_NCS(p) (p >> 28)
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/* Register bit fields and Masks */
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/* BDC Configuration 0 */
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#define BDC_PGS(p) (((p) & (0x7 << 8)) >> 8)
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#define BDC_SPB(p) (p & 0x7)
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/* BDC Capability1 */
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#define BDC_P64 (1 << 0)
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/* BDC Command register */
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#define BDC_CMD_FH 0xe
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#define BDC_CMD_DNC 0x6
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#define BDC_CMD_EPO 0x4
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#define BDC_CMD_BLA 0x3
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#define BDC_CMD_EPC 0x2
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#define BDC_CMD_DVC 0x1
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#define BDC_CMD_CWS (0x1 << 5)
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#define BDC_CMD_CST(p) (((p) & (0xf << 6))>>6)
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#define BDC_CMD_EPN(p) ((p & 0x1f) << 10)
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#define BDC_SUB_CMD_ADD (0x1 << 17)
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#define BDC_SUB_CMD_FWK (0x4 << 17)
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/* Reset sequence number */
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#define BDC_CMD_EPO_RST_SN (0x1 << 16)
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#define BDC_CMD_EP0_XSD (0x1 << 16)
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#define BDC_SUB_CMD_ADD_EP (0x1 << 17)
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#define BDC_SUB_CMD_DRP_EP (0x2 << 17)
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#define BDC_SUB_CMD_EP_STP (0x2 << 17)
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#define BDC_SUB_CMD_EP_STL (0x4 << 17)
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#define BDC_SUB_CMD_EP_RST (0x1 << 17)
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#define BDC_CMD_SRD (1 << 27)
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/* CMD completion status */
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#define BDC_CMDS_SUCC 0x1
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#define BDC_CMDS_PARA 0x3
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#define BDC_CMDS_STAT 0x4
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#define BDC_CMDS_FAIL 0x5
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#define BDC_CMDS_INTL 0x6
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#define BDC_CMDS_BUSY 0xf
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/* CMDSC Param 2 shifts */
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#define EPT_SHIFT 22
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#define MP_SHIFT 10
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#define MB_SHIFT 6
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#define EPM_SHIFT 4
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/* BDC USPSC */
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#define BDC_VBC (1 << 31)
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#define BDC_PRC (1 << 30)
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#define BDC_PCE (1 << 29)
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#define BDC_CFC (1 << 28)
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#define BDC_PCC (1 << 27)
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#define BDC_PSC (1 << 26)
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#define BDC_VBS (1 << 25)
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#define BDC_PRS (1 << 24)
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#define BDC_PCS (1 << 23)
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#define BDC_PSP(p) (((p) & (0x7 << 20))>>20)
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#define BDC_SCN (1 << 8)
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#define BDC_SDC (1 << 7)
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#define BDC_SWS (1 << 4)
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#define BDC_USPSC_RW (BDC_SCN|BDC_SDC|BDC_SWS|0xf)
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#define BDC_PSP(p) (((p) & (0x7 << 20))>>20)
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#define BDC_SPEED_FS 0x1
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#define BDC_SPEED_LS 0x2
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#define BDC_SPEED_HS 0x3
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#define BDC_SPEED_SS 0x4
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#define BDC_PST(p) (p & 0xf)
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#define BDC_PST_MASK 0xf
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/* USPPMS */
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#define BDC_U2E (0x1 << 31)
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#define BDC_U1E (0x1 << 30)
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#define BDC_U2A (0x1 << 29)
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#define BDC_PORT_W1S (0x1 << 17)
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#define BDC_U1T(p) ((p) & 0xff)
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#define BDC_U2T(p) (((p) & 0xff) << 8)
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#define BDC_U1T_MASK 0xff
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/* USBPM2 */
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/* Hardware LPM Enable */
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#define BDC_HLE (1 << 16)
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/* BDC Status and Control */
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#define BDC_COP_RST (1 << 29)
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#define BDC_COP_RUN (2 << 29)
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#define BDC_COP_STP (4 << 29)
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#define BDC_COP_MASK (BDC_COP_RST|BDC_COP_RUN|BDC_COP_STP)
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#define BDC_COS (1 << 28)
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#define BDC_CSTS(p) (((p) & (0x7 << 20)) >> 20)
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#define BDC_MASK_MCW (1 << 7)
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#define BDC_GIE (1 << 1)
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#define BDC_GIP (1 << 0)
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#define BDC_HLT 1
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#define BDC_NOR 2
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#define BDC_OIP 7
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/* Buffer descriptor and Status report bit fields and masks */
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#define BD_TYPE_BITMASK (0xf)
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#define BD_CHAIN 0xf
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#define BD_TFS_SHIFT 4
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#define BD_SOT (1 << 26)
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#define BD_EOT (1 << 27)
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#define BD_ISP (1 << 29)
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#define BD_IOC (1 << 30)
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#define BD_SBF (1 << 31)
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#define BD_INTR_TARGET(p) (((p) & 0x1f) << 27)
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#define BDC_SRR_RWS (1 << 4)
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#define BDC_SRR_RST (1 << 3)
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#define BDC_SRR_ISR (1 << 2)
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#define BDC_SRR_IE (1 << 1)
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#define BDC_SRR_IP (1 << 0)
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#define BDC_SRR_EPI(p) (((p) & (0xff << 24)) >> 24)
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#define BDC_SRR_DPI(p) (((p) & (0xff << 16)) >> 16)
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#define BDC_SRR_DPI_MASK 0x00ff0000
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#define MARK_CHAIN_BD (BD_CHAIN|BD_EOT|BD_SOT)
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/* Control transfer BD specific fields */
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#define BD_DIR_IN (1 << 25)
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#define BDC_PTC_MASK 0xf0000000
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/* status report defines */
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#define SR_XSF 0
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#define SR_USPC 4
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#define SR_BD_LEN(p) (p & 0xffffff)
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#define XSF_SUCC 0x1
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#define XSF_SHORT 0x3
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#define XSF_BABB 0x4
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#define XSF_SETUP_RECV 0x6
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#define XSF_DATA_START 0x7
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#define XSF_STATUS_START 0x8
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#define XSF_STS(p) (((p) >> 28) & 0xf)
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/* Transfer BD fields */
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#define BD_LEN(p) ((p) & 0x1ffff)
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#define BD_LTF (1 << 25)
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#define BD_TYPE_DS 0x1
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#define BD_TYPE_SS 0x2
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#define BDC_EP_ENABLED (1 << 0)
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#define BDC_EP_STALL (1 << 1)
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#define BDC_EP_STOP (1 << 2)
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/* One BD can transfer max 65536 bytes */
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#define BD_MAX_BUFF_SIZE (1 << 16)
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/* Maximum bytes in one XFR, Refer to BDC spec */
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#define MAX_XFR_LEN 16777215
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/* defines for Force Header command */
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#define DEV_NOTF_TYPE 6
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#define FWK_SUBTYPE 1
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#define TRA_PACKET 4
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#define to_bdc_ep(e) container_of(e, struct bdc_ep, usb_ep)
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#define to_bdc_req(r) container_of(r, struct bdc_req, usb_req)
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#define gadget_to_bdc(g) container_of(g, struct bdc, gadget)
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/* FUNCTION WAKE DEV NOTIFICATION interval, USB3 spec table 8.13 */
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#define BDC_TNOTIFY 2500 /*in ms*/
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/* Devstatus bitfields */
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#define REMOTE_WAKEUP_ISSUED (1 << 16)
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#define DEVICE_SUSPENDED (1 << 17)
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#define FUNC_WAKE_ISSUED (1 << 18)
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#define REMOTE_WAKE_ENABLE (1 << USB_DEVICE_REMOTE_WAKEUP)
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/* On disconnect, preserve these bits and clear rest */
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#define DEVSTATUS_CLEAR (1 << USB_DEVICE_SELF_POWERED)
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/* Hardware and software Data structures */
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/* Endpoint bd: buffer descriptor */
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struct bdc_bd {
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__le32 offset[4];
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};
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/* Status report in Status report ring(srr) */
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struct bdc_sr {
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__le32 offset[4];
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};
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/* bd_table: contiguous bd's in a table */
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struct bd_table {
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struct bdc_bd *start_bd;
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/* dma address of start bd of table*/
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dma_addr_t dma;
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};
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/*
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* Each endpoint has a bdl(buffer descriptor list), bdl consists of 1 or more bd
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* table's chained to each other through a chain bd, every table has equal
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* number of bds. the software uses bdi(bd index) to refer to particular bd in
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* the list.
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*/
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struct bd_list {
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/* Array of bd table pointers*/
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struct bd_table **bd_table_array;
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/* How many tables chained to each other */
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int num_tabs;
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/* Max_bdi = num_tabs * num_bds_table - 1 */
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int max_bdi;
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/* current enq bdi from sw point of view */
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int eqp_bdi;
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/* current deq bdi from sw point of view */
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int hwd_bdi;
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/* numbers of bds per table */
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int num_bds_table;
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};
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struct bdc_req;
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/* Representation of a transfer, one transfer can have multiple bd's */
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struct bd_transfer {
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struct bdc_req *req;
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/* start bd index */
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int start_bdi;
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/* this will be the next hw dqp when this transfer completes */
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int next_hwd_bdi;
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/* number of bds in this transfer */
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int num_bds;
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};
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/*
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* Representation of a gadget request, every gadget request is contained
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* by 1 bd_transfer.
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*/
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struct bdc_req {
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struct usb_request usb_req;
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struct list_head queue;
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struct bdc_ep *ep;
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/* only one Transfer per request */
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struct bd_transfer bd_xfr;
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int epnum;
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};
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/* scratchpad buffer needed by bdc hardware */
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struct bdc_scratchpad {
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dma_addr_t sp_dma;
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void *buff;
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u32 size;
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};
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/* endpoint representation */
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struct bdc_ep {
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|
struct usb_ep usb_ep;
|
||
|
|
struct list_head queue;
|
||
|
|
struct bdc *bdc;
|
||
|
|
u8 ep_type;
|
||
|
|
u8 dir;
|
||
|
|
u8 ep_num;
|
||
|
|
const struct usb_ss_ep_comp_descriptor *comp_desc;
|
||
|
|
const struct usb_endpoint_descriptor *desc;
|
||
|
|
unsigned int flags;
|
||
|
|
char name[20];
|
||
|
|
/* endpoint bd list*/
|
||
|
|
struct bd_list bd_list;
|
||
|
|
/*
|
||
|
|
* HW generates extra event for multi bd tranfers, this flag helps in
|
||
|
|
* ignoring the extra event
|
||
|
|
*/
|
||
|
|
bool ignore_next_sr;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* bdc cmmand parameter structure */
|
||
|
|
struct bdc_cmd_params {
|
||
|
|
u32 param2;
|
||
|
|
u32 param1;
|
||
|
|
u32 param0;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* status report ring(srr), currently one srr is supported for entire system */
|
||
|
|
struct srr {
|
||
|
|
struct bdc_sr *sr_bds;
|
||
|
|
u16 eqp_index;
|
||
|
|
u16 dqp_index;
|
||
|
|
dma_addr_t dma_addr;
|
||
|
|
};
|
||
|
|
|
||
|
|
/* EP0 states */
|
||
|
|
enum bdc_ep0_state {
|
||
|
|
WAIT_FOR_SETUP = 0,
|
||
|
|
WAIT_FOR_DATA_START,
|
||
|
|
WAIT_FOR_DATA_XMIT,
|
||
|
|
WAIT_FOR_STATUS_START,
|
||
|
|
WAIT_FOR_STATUS_XMIT,
|
||
|
|
STATUS_PENDING
|
||
|
|
};
|
||
|
|
|
||
|
|
/* Link states */
|
||
|
|
enum bdc_link_state {
|
||
|
|
BDC_LINK_STATE_U0 = 0x00,
|
||
|
|
BDC_LINK_STATE_U3 = 0x03,
|
||
|
|
BDC_LINK_STATE_RX_DET = 0x05,
|
||
|
|
BDC_LINK_STATE_RESUME = 0x0f
|
||
|
|
};
|
||
|
|
|
||
|
|
/* representation of bdc */
|
||
|
|
struct bdc {
|
||
|
|
struct usb_gadget gadget;
|
||
|
|
struct usb_gadget_driver *gadget_driver;
|
||
|
|
struct device *dev;
|
||
|
|
/* device lock */
|
||
|
|
spinlock_t lock;
|
||
|
|
|
||
|
|
/* generic phy */
|
||
|
|
struct phy **phys;
|
||
|
|
int num_phys;
|
||
|
|
/* num of endpoints for a particular instantiation of IP */
|
||
|
|
unsigned int num_eps;
|
||
|
|
/*
|
||
|
|
* Array of ep's, it uses the same index covention as bdc hw i.e.
|
||
|
|
* 1 for ep0, 2 for 1out,3 for 1in ....
|
||
|
|
*/
|
||
|
|
struct bdc_ep **bdc_ep_array;
|
||
|
|
void __iomem *regs;
|
||
|
|
struct bdc_scratchpad scratchpad;
|
||
|
|
u32 sp_buff_size;
|
||
|
|
/* current driver supports 1 status ring */
|
||
|
|
struct srr srr;
|
||
|
|
/* Last received setup packet */
|
||
|
|
struct usb_ctrlrequest setup_pkt;
|
||
|
|
struct bdc_req ep0_req;
|
||
|
|
struct bdc_req status_req;
|
||
|
|
enum bdc_ep0_state ep0_state;
|
||
|
|
bool delayed_status;
|
||
|
|
bool zlp_needed;
|
||
|
|
bool reinit;
|
||
|
|
bool pullup;
|
||
|
|
/* Bits 0-15 are standard and 16-31 for proprietary information */
|
||
|
|
u32 devstatus;
|
||
|
|
int irq;
|
||
|
|
void *mem;
|
||
|
|
u32 dev_addr;
|
||
|
|
/* DMA pools */
|
||
|
|
struct dma_pool *bd_table_pool;
|
||
|
|
u8 test_mode;
|
||
|
|
/* array of callbacks for various status report handlers */
|
||
|
|
void (*sr_handler[2])(struct bdc *, struct bdc_sr *);
|
||
|
|
/* ep0 callback handlers */
|
||
|
|
void (*sr_xsf_ep0[3])(struct bdc *, struct bdc_sr *);
|
||
|
|
/* ep0 response buffer for ch9 requests like GET_STATUS and SET_SEL */
|
||
|
|
unsigned char ep0_response_buff[EP0_RESPONSE_BUFF];
|
||
|
|
/*
|
||
|
|
* Timer to check if host resumed transfer after bdc sent Func wake
|
||
|
|
* notification packet after a remote wakeup. if not, then resend the
|
||
|
|
* Func Wake packet every 2.5 secs. Refer to USB3 spec section 8.5.6.4
|
||
|
|
*/
|
||
|
|
struct delayed_work func_wake_notify;
|
||
|
|
struct clk *clk;
|
||
|
|
};
|
||
|
|
|
||
|
|
static inline u32 bdc_readl(void __iomem *base, u32 offset)
|
||
|
|
{
|
||
|
|
return readl(base + offset);
|
||
|
|
}
|
||
|
|
|
||
|
|
static inline void bdc_writel(void __iomem *base, u32 offset, u32 value)
|
||
|
|
{
|
||
|
|
writel(value, base + offset);
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Buffer descriptor list operations */
|
||
|
|
void bdc_notify_xfr(struct bdc *, u32);
|
||
|
|
void bdc_softconn(struct bdc *);
|
||
|
|
void bdc_softdisconn(struct bdc *);
|
||
|
|
int bdc_run(struct bdc *);
|
||
|
|
int bdc_stop(struct bdc *);
|
||
|
|
int bdc_reset(struct bdc *);
|
||
|
|
int bdc_udc_init(struct bdc *);
|
||
|
|
void bdc_udc_exit(struct bdc *);
|
||
|
|
int bdc_reinit(struct bdc *);
|
||
|
|
|
||
|
|
/* Status report handlers */
|
||
|
|
/* Upstream port status change sr */
|
||
|
|
void bdc_sr_uspc(struct bdc *, struct bdc_sr *);
|
||
|
|
/* transfer sr */
|
||
|
|
void bdc_sr_xsf(struct bdc *, struct bdc_sr *);
|
||
|
|
/* EP0 XSF handlers */
|
||
|
|
void bdc_xsf_ep0_setup_recv(struct bdc *, struct bdc_sr *);
|
||
|
|
void bdc_xsf_ep0_data_start(struct bdc *, struct bdc_sr *);
|
||
|
|
void bdc_xsf_ep0_status_start(struct bdc *, struct bdc_sr *);
|
||
|
|
|
||
|
|
#endif /* __LINUX_BDC_H__ */
|