355 lines
11 KiB
C
355 lines
11 KiB
C
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/******************************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2007 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*
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* Contact Information:
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* Intel Linux Wireless <linuxwifi@intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
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* Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
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* Copyright(c) 2016 - 2017 Intel Deutschland GmbH
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*****************************************************************************/
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#ifndef __iwl_fw_api_debug_h__
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#define __iwl_fw_api_debug_h__
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/**
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* enum iwl_debug_cmds - debug commands
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*/
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enum iwl_debug_cmds {
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/**
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* @LMAC_RD_WR:
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* LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
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* &struct iwl_dbg_mem_access_rsp
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*/
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LMAC_RD_WR = 0x0,
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/**
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* @UMAC_RD_WR:
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* UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and
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* &struct iwl_dbg_mem_access_rsp
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*/
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UMAC_RD_WR = 0x1,
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/**
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* @MFU_ASSERT_DUMP_NTF:
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* &struct iwl_mfu_assert_dump_notif
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*/
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MFU_ASSERT_DUMP_NTF = 0xFE,
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};
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/* Error response/notification */
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enum {
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FW_ERR_UNKNOWN_CMD = 0x0,
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FW_ERR_INVALID_CMD_PARAM = 0x1,
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FW_ERR_SERVICE = 0x2,
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FW_ERR_ARC_MEMORY = 0x3,
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FW_ERR_ARC_CODE = 0x4,
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FW_ERR_WATCH_DOG = 0x5,
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FW_ERR_WEP_GRP_KEY_INDX = 0x10,
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FW_ERR_WEP_KEY_SIZE = 0x11,
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FW_ERR_OBSOLETE_FUNC = 0x12,
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FW_ERR_UNEXPECTED = 0xFE,
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FW_ERR_FATAL = 0xFF
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};
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/**
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* struct iwl_error_resp - FW error indication
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* ( REPLY_ERROR = 0x2 )
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* @error_type: one of FW_ERR_*
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* @cmd_id: the command ID for which the error occurred
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* @reserved1: reserved
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* @bad_cmd_seq_num: sequence number of the erroneous command
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* @error_service: which service created the error, applicable only if
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* error_type = 2, otherwise 0
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* @timestamp: TSF in usecs.
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*/
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struct iwl_error_resp {
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__le32 error_type;
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u8 cmd_id;
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u8 reserved1;
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__le16 bad_cmd_seq_num;
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__le32 error_service;
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__le64 timestamp;
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} __packed;
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#define TX_FIFO_MAX_NUM_9000 8
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#define TX_FIFO_MAX_NUM 15
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#define RX_FIFO_MAX_NUM 2
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#define TX_FIFO_INTERNAL_MAX_NUM 6
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/**
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* struct iwl_shared_mem_cfg_v2 - Shared memory configuration information
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*
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* @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not
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* accessible)
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* @shared_mem_size: shared memory size
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* @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to
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* 0x0 as accessible only via DBGM RDAT)
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* @sample_buff_size: internal sample buff size
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* @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre
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* 8000 HW set to 0x0 as not accessible)
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* @txfifo_size: size of TXF0 ... TXF7
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* @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0
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* @page_buff_addr: used by UMAC and performance debug (page miss analysis),
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* when paging is not supported this should be 0
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* @page_buff_size: size of %page_buff_addr
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* @rxfifo_addr: Start address of rxFifo
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* @internal_txfifo_addr: start address of internalFifo
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* @internal_txfifo_size: internal fifos' size
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*
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* NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG
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* set, the last 3 members don't exist.
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*/
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struct iwl_shared_mem_cfg_v2 {
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__le32 shared_mem_addr;
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__le32 shared_mem_size;
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__le32 sample_buff_addr;
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__le32 sample_buff_size;
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__le32 txfifo_addr;
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__le32 txfifo_size[TX_FIFO_MAX_NUM_9000];
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__le32 rxfifo_size[RX_FIFO_MAX_NUM];
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__le32 page_buff_addr;
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__le32 page_buff_size;
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__le32 rxfifo_addr;
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__le32 internal_txfifo_addr;
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__le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM];
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} __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */
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/**
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* struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration
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*
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* @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB)
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* @txfifo_size: size of TX FIFOs
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* @rxfifo1_addr: RXF1 addr
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* @rxfifo1_size: RXF1 size
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*/
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struct iwl_shared_mem_lmac_cfg {
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__le32 txfifo_addr;
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__le32 txfifo_size[TX_FIFO_MAX_NUM];
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__le32 rxfifo1_addr;
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__le32 rxfifo1_size;
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} __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */
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/**
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* struct iwl_shared_mem_cfg - Shared memory configuration information
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*
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* @shared_mem_addr: shared memory address
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* @shared_mem_size: shared memory size
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* @sample_buff_addr: internal sample (mon/adc) buff addr
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* @sample_buff_size: internal sample buff size
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* @rxfifo2_addr: start addr of RXF2
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* @rxfifo2_size: size of RXF2
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* @page_buff_addr: used by UMAC and performance debug (page miss analysis),
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* when paging is not supported this should be 0
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* @page_buff_size: size of %page_buff_addr
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* @lmac_num: number of LMACs (1 or 2)
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* @lmac_smem: per - LMAC smem data
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*/
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struct iwl_shared_mem_cfg {
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__le32 shared_mem_addr;
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__le32 shared_mem_size;
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__le32 sample_buff_addr;
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__le32 sample_buff_size;
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__le32 rxfifo2_addr;
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__le32 rxfifo2_size;
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__le32 page_buff_addr;
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__le32 page_buff_size;
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__le32 lmac_num;
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struct iwl_shared_mem_lmac_cfg lmac_smem[2];
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} __packed; /* SHARED_MEM_ALLOC_API_S_VER_3 */
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/**
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* struct iwl_mfuart_load_notif - mfuart image version & status
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* ( MFUART_LOAD_NOTIFICATION = 0xb1 )
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* @installed_ver: installed image version
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* @external_ver: external image version
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* @status: MFUART loading status
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* @duration: MFUART loading time
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* @image_size: MFUART image size in bytes
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*/
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struct iwl_mfuart_load_notif {
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__le32 installed_ver;
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__le32 external_ver;
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__le32 status;
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__le32 duration;
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/* image size valid only in v2 of the command */
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__le32 image_size;
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} __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */
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/**
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* struct iwl_mfu_assert_dump_notif - mfuart dump logs
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* ( MFU_ASSERT_DUMP_NTF = 0xfe )
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* @assert_id: mfuart assert id that cause the notif
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* @curr_reset_num: number of asserts since uptime
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* @index_num: current chunk id
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* @parts_num: total number of chunks
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* @data_size: number of data bytes sent
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* @data: data buffer
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*/
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struct iwl_mfu_assert_dump_notif {
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__le32 assert_id;
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__le32 curr_reset_num;
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__le16 index_num;
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__le16 parts_num;
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__le32 data_size;
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__le32 data[0];
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} __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */
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/**
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* enum iwl_mvm_marker_id - marker ids
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*
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* The ids for different type of markers to insert into the usniffer logs
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*
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* @MARKER_ID_TX_FRAME_LATENCY: TX latency marker
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*/
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enum iwl_mvm_marker_id {
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MARKER_ID_TX_FRAME_LATENCY = 1,
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}; /* MARKER_ID_API_E_VER_1 */
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/**
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* struct iwl_mvm_marker - mark info into the usniffer logs
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*
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* (MARKER_CMD = 0xcb)
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*
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* Mark the UTC time stamp into the usniffer logs together with additional
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* metadata, so the usniffer output can be parsed.
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* In the command response the ucode will return the GP2 time.
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*
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* @dw_len: The amount of dwords following this byte including this byte.
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* @marker_id: A unique marker id (iwl_mvm_marker_id).
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* @reserved: reserved.
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* @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC
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* @metadata: additional meta data that will be written to the unsiffer log
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*/
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struct iwl_mvm_marker {
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u8 dw_len;
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u8 marker_id;
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__le16 reserved;
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__le64 timestamp;
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__le32 metadata[0];
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} __packed; /* MARKER_API_S_VER_1 */
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/**
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* struct iwl_mvm_marker_rsp - Response to marker cmd
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*
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* @gp2: The gp2 clock value in the FW
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*/
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struct iwl_mvm_marker_rsp {
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__le32 gp2;
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} __packed;
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/* Operation types for the debug mem access */
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enum {
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DEBUG_MEM_OP_READ = 0,
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DEBUG_MEM_OP_WRITE = 1,
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DEBUG_MEM_OP_WRITE_BYTES = 2,
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};
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#define DEBUG_MEM_MAX_SIZE_DWORDS 32
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/**
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* struct iwl_dbg_mem_access_cmd - Request the device to read/write memory
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* @op: DEBUG_MEM_OP_*
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* @addr: address to read/write from/to
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* @len: in dwords, to read/write
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* @data: for write opeations, contains the source buffer
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*/
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struct iwl_dbg_mem_access_cmd {
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__le32 op;
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__le32 addr;
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__le32 len;
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__le32 data[];
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} __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */
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/* Status responses for the debug mem access */
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enum {
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DEBUG_MEM_STATUS_SUCCESS = 0x0,
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DEBUG_MEM_STATUS_FAILED = 0x1,
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DEBUG_MEM_STATUS_LOCKED = 0x2,
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DEBUG_MEM_STATUS_HIDDEN = 0x3,
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DEBUG_MEM_STATUS_LENGTH = 0x4,
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};
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/**
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* struct iwl_dbg_mem_access_rsp - Response to debug mem commands
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* @status: DEBUG_MEM_STATUS_*
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* @len: read dwords (0 for write operations)
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* @data: contains the read DWs
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*/
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struct iwl_dbg_mem_access_rsp {
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__le32 status;
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__le32 len;
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__le32 data[];
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} __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */
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#define CONT_REC_COMMAND_SIZE 80
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#define ENABLE_CONT_RECORDING 0x15
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#define DISABLE_CONT_RECORDING 0x16
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/*
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* struct iwl_continuous_record_mode - recording mode
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*/
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struct iwl_continuous_record_mode {
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__le16 enable_recording;
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} __packed;
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/*
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* struct iwl_continuous_record_cmd - enable/disable continuous recording
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*/
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struct iwl_continuous_record_cmd {
|
||
|
|
struct iwl_continuous_record_mode record_mode;
|
||
|
|
u8 pad[CONT_REC_COMMAND_SIZE -
|
||
|
|
sizeof(struct iwl_continuous_record_mode)];
|
||
|
|
} __packed;
|
||
|
|
|
||
|
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#endif /* __iwl_fw_api_debug_h__ */
|