389 lines
9.3 KiB
C
389 lines
9.3 KiB
C
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/*
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* Copyright (C) 2015-2017 Broadcom
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "bcm-phy-lib.h"
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#include <linux/brcmphy.h>
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#include <linux/export.h>
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#include <linux/mdio.h>
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#include <linux/module.h>
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#include <linux/phy.h>
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#include <linux/ethtool.h>
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#define MII_BCM_CHANNEL_WIDTH 0x2000
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#define BCM_CL45VEN_EEE_ADV 0x3c
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int bcm_phy_write_exp(struct phy_device *phydev, u16 reg, u16 val)
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{
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int rc;
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rc = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
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if (rc < 0)
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return rc;
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return phy_write(phydev, MII_BCM54XX_EXP_DATA, val);
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}
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EXPORT_SYMBOL_GPL(bcm_phy_write_exp);
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int bcm_phy_read_exp(struct phy_device *phydev, u16 reg)
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{
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int val;
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val = phy_write(phydev, MII_BCM54XX_EXP_SEL, reg);
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if (val < 0)
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return val;
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val = phy_read(phydev, MII_BCM54XX_EXP_DATA);
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/* Restore default value. It's O.K. if this write fails. */
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phy_write(phydev, MII_BCM54XX_EXP_SEL, 0);
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return val;
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}
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EXPORT_SYMBOL_GPL(bcm_phy_read_exp);
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int bcm54xx_auxctl_read(struct phy_device *phydev, u16 regnum)
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{
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/* The register must be written to both the Shadow Register Select and
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* the Shadow Read Register Selector
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*/
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phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum |
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regnum << MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT);
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return phy_read(phydev, MII_BCM54XX_AUX_CTL);
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}
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EXPORT_SYMBOL_GPL(bcm54xx_auxctl_read);
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int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
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{
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return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
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}
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EXPORT_SYMBOL(bcm54xx_auxctl_write);
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int bcm_phy_write_misc(struct phy_device *phydev,
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u16 reg, u16 chl, u16 val)
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{
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int rc;
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int tmp;
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rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
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MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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if (rc < 0)
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return rc;
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tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
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tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
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rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
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if (rc < 0)
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return rc;
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tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
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rc = bcm_phy_write_exp(phydev, tmp, val);
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return rc;
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}
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EXPORT_SYMBOL_GPL(bcm_phy_write_misc);
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int bcm_phy_read_misc(struct phy_device *phydev,
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u16 reg, u16 chl)
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{
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int rc;
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int tmp;
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rc = phy_write(phydev, MII_BCM54XX_AUX_CTL,
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MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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if (rc < 0)
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return rc;
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tmp = phy_read(phydev, MII_BCM54XX_AUX_CTL);
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tmp |= MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA;
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rc = phy_write(phydev, MII_BCM54XX_AUX_CTL, tmp);
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if (rc < 0)
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return rc;
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tmp = (chl * MII_BCM_CHANNEL_WIDTH) | reg;
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rc = bcm_phy_read_exp(phydev, tmp);
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return rc;
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}
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EXPORT_SYMBOL_GPL(bcm_phy_read_misc);
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int bcm_phy_ack_intr(struct phy_device *phydev)
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{
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int reg;
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/* Clear pending interrupts. */
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reg = phy_read(phydev, MII_BCM54XX_ISR);
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if (reg < 0)
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return reg;
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return 0;
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}
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EXPORT_SYMBOL_GPL(bcm_phy_ack_intr);
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int bcm_phy_config_intr(struct phy_device *phydev)
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{
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int reg;
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reg = phy_read(phydev, MII_BCM54XX_ECR);
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if (reg < 0)
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return reg;
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if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
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reg &= ~MII_BCM54XX_ECR_IM;
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else
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reg |= MII_BCM54XX_ECR_IM;
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return phy_write(phydev, MII_BCM54XX_ECR, reg);
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}
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EXPORT_SYMBOL_GPL(bcm_phy_config_intr);
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int bcm_phy_read_shadow(struct phy_device *phydev, u16 shadow)
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{
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phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
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return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
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}
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EXPORT_SYMBOL_GPL(bcm_phy_read_shadow);
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int bcm_phy_write_shadow(struct phy_device *phydev, u16 shadow,
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u16 val)
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{
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return phy_write(phydev, MII_BCM54XX_SHD,
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MII_BCM54XX_SHD_WRITE |
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MII_BCM54XX_SHD_VAL(shadow) |
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MII_BCM54XX_SHD_DATA(val));
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}
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EXPORT_SYMBOL_GPL(bcm_phy_write_shadow);
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int bcm_phy_enable_apd(struct phy_device *phydev, bool dll_pwr_down)
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{
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int val;
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if (dll_pwr_down) {
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val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR3);
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if (val < 0)
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return val;
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val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
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bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR3, val);
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}
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val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_APD);
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if (val < 0)
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return val;
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/* Clear APD bits */
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val &= BCM_APD_CLR_MASK;
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if (phydev->autoneg == AUTONEG_ENABLE)
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val |= BCM54XX_SHD_APD_EN;
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else
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val |= BCM_NO_ANEG_APD_EN;
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/* Enable energy detect single link pulse for easy wakeup */
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val |= BCM_APD_SINGLELP_EN;
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/* Enable Auto Power-Down (APD) for the PHY */
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return bcm_phy_write_shadow(phydev, BCM54XX_SHD_APD, val);
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}
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EXPORT_SYMBOL_GPL(bcm_phy_enable_apd);
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int bcm_phy_set_eee(struct phy_device *phydev, bool enable)
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{
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int val;
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/* Enable EEE at PHY level */
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val = phy_read_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL);
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if (val < 0)
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return val;
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if (enable)
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val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
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else
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val &= ~(LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X);
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phy_write_mmd(phydev, MDIO_MMD_AN, BRCM_CL45VEN_EEE_CONTROL, (u32)val);
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/* Advertise EEE */
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val = phy_read_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV);
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if (val < 0)
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return val;
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if (enable)
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val |= (MDIO_EEE_100TX | MDIO_EEE_1000T);
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else
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val &= ~(MDIO_EEE_100TX | MDIO_EEE_1000T);
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phy_write_mmd(phydev, MDIO_MMD_AN, BCM_CL45VEN_EEE_ADV, (u32)val);
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return 0;
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}
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EXPORT_SYMBOL_GPL(bcm_phy_set_eee);
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int bcm_phy_downshift_get(struct phy_device *phydev, u8 *count)
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{
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int val;
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val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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if (val < 0)
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return val;
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/* Check if wirespeed is enabled or not */
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if (!(val & MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN)) {
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*count = DOWNSHIFT_DEV_DISABLE;
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return 0;
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}
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val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
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if (val < 0)
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return val;
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/* Downgrade after one link attempt */
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if (val & BCM54XX_SHD_SCR2_WSPD_RTRY_DIS) {
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*count = 1;
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} else {
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/* Downgrade after configured retry count */
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val >>= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
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val &= BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK;
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*count = val + BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET;
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}
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return 0;
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}
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EXPORT_SYMBOL_GPL(bcm_phy_downshift_get);
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int bcm_phy_downshift_set(struct phy_device *phydev, u8 count)
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{
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int val = 0, ret = 0;
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/* Range check the number given */
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if (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET >
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BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK &&
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count != DOWNSHIFT_DEV_DEFAULT_COUNT) {
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return -ERANGE;
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}
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val = bcm54xx_auxctl_read(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC);
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if (val < 0)
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return val;
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/* Se the write enable bit */
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val |= MII_BCM54XX_AUXCTL_MISC_WREN;
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if (count == DOWNSHIFT_DEV_DISABLE) {
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val &= ~MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
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return bcm54xx_auxctl_write(phydev,
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MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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val);
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} else {
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val |= MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN;
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ret = bcm54xx_auxctl_write(phydev,
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MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
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val);
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if (ret < 0)
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return ret;
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}
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val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_SCR2);
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val &= ~(BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK <<
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BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT |
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BCM54XX_SHD_SCR2_WSPD_RTRY_DIS);
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switch (count) {
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case 1:
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val |= BCM54XX_SHD_SCR2_WSPD_RTRY_DIS;
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break;
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case DOWNSHIFT_DEV_DEFAULT_COUNT:
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val |= 1 << BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
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break;
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default:
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val |= (count - BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET) <<
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BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT;
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break;
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}
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return bcm_phy_write_shadow(phydev, BCM54XX_SHD_SCR2, val);
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}
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EXPORT_SYMBOL_GPL(bcm_phy_downshift_set);
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struct bcm_phy_hw_stat {
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const char *string;
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u8 reg;
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u8 shift;
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u8 bits;
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};
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/* Counters freeze at either 0xffff or 0xff, better than nothing */
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static const struct bcm_phy_hw_stat bcm_phy_hw_stats[] = {
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{ "phy_receive_errors", MII_BRCM_CORE_BASE12, 0, 16 },
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{ "phy_serdes_ber_errors", MII_BRCM_CORE_BASE13, 8, 8 },
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{ "phy_false_carrier_sense_errors", MII_BRCM_CORE_BASE13, 0, 8 },
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{ "phy_local_rcvr_nok", MII_BRCM_CORE_BASE14, 8, 8 },
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{ "phy_remote_rcv_nok", MII_BRCM_CORE_BASE14, 0, 8 },
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};
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int bcm_phy_get_sset_count(struct phy_device *phydev)
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{
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return ARRAY_SIZE(bcm_phy_hw_stats);
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}
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EXPORT_SYMBOL_GPL(bcm_phy_get_sset_count);
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void bcm_phy_get_strings(struct phy_device *phydev, u8 *data)
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{
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
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memcpy(data + i * ETH_GSTRING_LEN,
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bcm_phy_hw_stats[i].string, ETH_GSTRING_LEN);
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}
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EXPORT_SYMBOL_GPL(bcm_phy_get_strings);
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#ifndef UINT64_MAX
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#define UINT64_MAX (u64)(~((u64)0))
|
||
|
|
#endif
|
||
|
|
|
||
|
|
/* Caller is supposed to provide appropriate storage for the library code to
|
||
|
|
* access the shadow copy
|
||
|
|
*/
|
||
|
|
static u64 bcm_phy_get_stat(struct phy_device *phydev, u64 *shadow,
|
||
|
|
unsigned int i)
|
||
|
|
{
|
||
|
|
struct bcm_phy_hw_stat stat = bcm_phy_hw_stats[i];
|
||
|
|
int val;
|
||
|
|
u64 ret;
|
||
|
|
|
||
|
|
val = phy_read(phydev, stat.reg);
|
||
|
|
if (val < 0) {
|
||
|
|
ret = UINT64_MAX;
|
||
|
|
} else {
|
||
|
|
val >>= stat.shift;
|
||
|
|
val = val & ((1 << stat.bits) - 1);
|
||
|
|
shadow[i] += val;
|
||
|
|
ret = shadow[i];
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
void bcm_phy_get_stats(struct phy_device *phydev, u64 *shadow,
|
||
|
|
struct ethtool_stats *stats, u64 *data)
|
||
|
|
{
|
||
|
|
unsigned int i;
|
||
|
|
|
||
|
|
for (i = 0; i < ARRAY_SIZE(bcm_phy_hw_stats); i++)
|
||
|
|
data[i] = bcm_phy_get_stat(phydev, shadow, i);
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(bcm_phy_get_stats);
|
||
|
|
|
||
|
|
MODULE_DESCRIPTION("Broadcom PHY Library");
|
||
|
|
MODULE_LICENSE("GPL v2");
|
||
|
|
MODULE_AUTHOR("Broadcom Corporation");
|