288 lines
9.2 KiB
C
288 lines
9.2 KiB
C
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/*
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* This file is part of the Chelsio T4 Ethernet driver for Linux.
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*
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* Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __T4_HW_H
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#define __T4_HW_H
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#include <linux/types.h>
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enum {
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NCHAN = 4, /* # of HW channels */
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MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
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EEPROMSIZE = 17408, /* Serial EEPROM physical size */
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EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
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EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
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RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
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TCB_SIZE = 128, /* TCB size */
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NMTUS = 16, /* size of MTU table */
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NCCTRL_WIN = 32, /* # of congestion control windows */
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NTX_SCHED = 8, /* # of HW Tx scheduling queues */
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PM_NSTATS = 5, /* # of PM stats */
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T6_PM_NSTATS = 7, /* # of PM stats in T6 */
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MBOX_LEN = 64, /* mailbox size in bytes */
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TRACE_LEN = 112, /* length of trace data and mask */
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FILTER_OPT_LEN = 36, /* filter tuple width for optional components */
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};
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enum {
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CIM_NUM_IBQ = 6, /* # of CIM IBQs */
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CIM_NUM_OBQ = 6, /* # of CIM OBQs */
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CIM_NUM_OBQ_T5 = 8, /* # of CIM OBQs for T5 adapter */
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CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
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CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
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CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
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CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
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CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */
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TPLA_SIZE = 128, /* # of 64-bit words in TP LA */
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ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */
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};
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/* SGE context types */
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enum ctxt_type {
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CTXT_FLM = 2,
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CTXT_CNM,
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};
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enum {
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SF_PAGE_SIZE = 256, /* serial flash page size */
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SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
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};
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enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
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enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
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enum {
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SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
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SGE_CTXT_SIZE = 24, /* size of SGE context */
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SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
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SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
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SGE_MAX_IQ_SIZE = 65520,
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SGE_TIMER_RSTRT_CNTR = 6, /* restart RX packet threshold counter */
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SGE_TIMER_UPD_CIDX = 7, /* update cidx only */
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SGE_EQ_IDXSIZE = 64, /* egress queue pidx/cidx unit size */
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SGE_INTRDST_PCI = 0, /* interrupt destination is PCI-E */
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SGE_INTRDST_IQ = 1, /* destination is an ingress queue */
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SGE_UPDATEDEL_NONE = 0, /* ingress queue pidx update delivery */
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SGE_UPDATEDEL_INTR = 1, /* interrupt */
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SGE_UPDATEDEL_STPG = 2, /* status page */
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SGE_UPDATEDEL_BOTH = 3, /* interrupt and status page */
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SGE_HOSTFCMODE_NONE = 0, /* egress queue cidx updates */
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SGE_HOSTFCMODE_IQ = 1, /* sent to ingress queue */
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SGE_HOSTFCMODE_STPG = 2, /* sent to status page */
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SGE_HOSTFCMODE_BOTH = 3, /* ingress queue and status page */
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SGE_FETCHBURSTMIN_16B = 0,/* egress queue descriptor fetch minimum */
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SGE_FETCHBURSTMIN_32B = 1,
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SGE_FETCHBURSTMIN_64B = 2,
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SGE_FETCHBURSTMIN_128B = 3,
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SGE_FETCHBURSTMAX_64B = 0,/* egress queue descriptor fetch maximum */
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SGE_FETCHBURSTMAX_128B = 1,
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SGE_FETCHBURSTMAX_256B = 2,
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SGE_FETCHBURSTMAX_512B = 3,
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SGE_CIDXFLUSHTHRESH_1 = 0,/* egress queue cidx flush threshold */
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SGE_CIDXFLUSHTHRESH_2 = 1,
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SGE_CIDXFLUSHTHRESH_4 = 2,
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SGE_CIDXFLUSHTHRESH_8 = 3,
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SGE_CIDXFLUSHTHRESH_16 = 4,
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SGE_CIDXFLUSHTHRESH_32 = 5,
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SGE_CIDXFLUSHTHRESH_64 = 6,
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SGE_CIDXFLUSHTHRESH_128 = 7,
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SGE_INGPADBOUNDARY_SHIFT = 5,/* ingress queue pad boundary */
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};
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/* PCI-e memory window access */
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enum pcie_memwin {
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MEMWIN_NIC = 0,
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MEMWIN_RSVD1 = 1,
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MEMWIN_RSVD2 = 2,
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MEMWIN_RDMA = 3,
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MEMWIN_RSVD4 = 4,
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MEMWIN_FOISCSI = 5,
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MEMWIN_CSIOSTOR = 6,
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MEMWIN_RSVD7 = 7,
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};
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struct sge_qstat { /* data written to SGE queue status entries */
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__be32 qid;
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__be16 cidx;
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__be16 pidx;
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};
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/*
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* Structure for last 128 bits of response descriptors
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*/
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struct rsp_ctrl {
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__be32 hdrbuflen_pidx;
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__be32 pldbuflen_qid;
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union {
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u8 type_gen;
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__be64 last_flit;
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};
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};
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#define RSPD_NEWBUF_S 31
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#define RSPD_NEWBUF_V(x) ((x) << RSPD_NEWBUF_S)
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#define RSPD_NEWBUF_F RSPD_NEWBUF_V(1U)
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#define RSPD_LEN_S 0
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#define RSPD_LEN_M 0x7fffffff
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#define RSPD_LEN_G(x) (((x) >> RSPD_LEN_S) & RSPD_LEN_M)
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#define RSPD_QID_S RSPD_LEN_S
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#define RSPD_QID_M RSPD_LEN_M
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#define RSPD_QID_G(x) RSPD_LEN_G(x)
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#define RSPD_GEN_S 7
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#define RSPD_TYPE_S 4
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#define RSPD_TYPE_M 0x3
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#define RSPD_TYPE_G(x) (((x) >> RSPD_TYPE_S) & RSPD_TYPE_M)
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/* Rx queue interrupt deferral fields: counter enable and timer index */
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#define QINTR_CNT_EN_S 0
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#define QINTR_CNT_EN_V(x) ((x) << QINTR_CNT_EN_S)
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#define QINTR_CNT_EN_F QINTR_CNT_EN_V(1U)
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#define QINTR_TIMER_IDX_S 1
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#define QINTR_TIMER_IDX_M 0x7
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#define QINTR_TIMER_IDX_V(x) ((x) << QINTR_TIMER_IDX_S)
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#define QINTR_TIMER_IDX_G(x) (((x) >> QINTR_TIMER_IDX_S) & QINTR_TIMER_IDX_M)
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/*
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* Flash layout.
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*/
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#define FLASH_START(start) ((start) * SF_SEC_SIZE)
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#define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
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enum {
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/*
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* Various Expansion-ROM boot images, etc.
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*/
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FLASH_EXP_ROM_START_SEC = 0,
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FLASH_EXP_ROM_NSECS = 6,
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FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
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FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
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/*
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* iSCSI Boot Firmware Table (iBFT) and other driver-related
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* parameters ...
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*/
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FLASH_IBFT_START_SEC = 6,
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FLASH_IBFT_NSECS = 1,
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FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
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FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
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/*
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* Boot configuration data.
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*/
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FLASH_BOOTCFG_START_SEC = 7,
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FLASH_BOOTCFG_NSECS = 1,
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FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
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FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
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/*
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* Location of firmware image in FLASH.
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*/
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FLASH_FW_START_SEC = 8,
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FLASH_FW_NSECS = 16,
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FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
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FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
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/* Location of bootstrap firmware image in FLASH.
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*/
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FLASH_FWBOOTSTRAP_START_SEC = 27,
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FLASH_FWBOOTSTRAP_NSECS = 1,
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FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
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FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
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/*
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* iSCSI persistent/crash information.
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*/
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FLASH_ISCSI_CRASH_START_SEC = 29,
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FLASH_ISCSI_CRASH_NSECS = 1,
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FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
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FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
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/*
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* FCoE persistent/crash information.
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*/
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FLASH_FCOE_CRASH_START_SEC = 30,
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FLASH_FCOE_CRASH_NSECS = 1,
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FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
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FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
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/*
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* Location of Firmware Configuration File in FLASH. Since the FPGA
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* "FLASH" is smaller we need to store the Configuration File in a
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* different location -- which will overlap the end of the firmware
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* image if firmware ever gets that large ...
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*/
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FLASH_CFG_START_SEC = 31,
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FLASH_CFG_NSECS = 1,
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FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
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FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
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/* We don't support FLASH devices which can't support the full
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* standard set of sections which we need for normal
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* operations.
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*/
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FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
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FLASH_FPGA_CFG_START_SEC = 15,
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FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
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/*
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* Sectors 32-63 are reserved for FLASH failover.
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*/
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};
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#undef FLASH_START
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#undef FLASH_MAX_SIZE
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#define SGE_TIMESTAMP_S 0
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#define SGE_TIMESTAMP_M 0xfffffffffffffffULL
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#define SGE_TIMESTAMP_V(x) ((__u64)(x) << SGE_TIMESTAMP_S)
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#define SGE_TIMESTAMP_G(x) (((__u64)(x) >> SGE_TIMESTAMP_S) & SGE_TIMESTAMP_M)
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#endif /* __T4_HW_H */
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