385 lines
9.7 KiB
C
385 lines
9.7 KiB
C
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/*
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* Copyright (C) 2017 Chelsio Communications. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* The full GNU General Public License is included in this distribution in
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* the file called "COPYING".
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*
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*/
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#ifndef __CUDBG_ENTITY_H__
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#define __CUDBG_ENTITY_H__
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#define EDC0_FLAG 3
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#define EDC1_FLAG 4
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#define CUDBG_ENTITY_SIGNATURE 0xCCEDB001
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struct card_mem {
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u16 size_edc0;
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u16 size_edc1;
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u16 mem_flag;
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};
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struct cudbg_mbox_log {
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struct mbox_cmd entry;
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u32 hi[MBOX_LEN / 8];
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u32 lo[MBOX_LEN / 8];
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};
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struct cudbg_cim_qcfg {
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u8 chip;
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u16 base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
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u16 size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
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u16 thres[CIM_NUM_IBQ];
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u32 obq_wr[2 * CIM_NUM_OBQ_T5];
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u32 stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)];
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};
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struct cudbg_rss_vf_conf {
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u32 rss_vf_vfl;
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u32 rss_vf_vfh;
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};
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struct cudbg_pm_stats {
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u32 tx_cnt[T6_PM_NSTATS];
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u32 rx_cnt[T6_PM_NSTATS];
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u64 tx_cyc[T6_PM_NSTATS];
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u64 rx_cyc[T6_PM_NSTATS];
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};
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struct cudbg_hw_sched {
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u32 kbps[NTX_SCHED];
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u32 ipg[NTX_SCHED];
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u32 pace_tab[NTX_SCHED];
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u32 mode;
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u32 map;
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};
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struct ireg_field {
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u32 ireg_addr;
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u32 ireg_data;
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u32 ireg_local_offset;
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u32 ireg_offset_range;
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};
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struct ireg_buf {
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struct ireg_field tp_pio;
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u32 outbuf[32];
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};
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struct cudbg_ulprx_la {
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u32 data[ULPRX_LA_SIZE * 8];
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u32 size;
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};
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struct cudbg_tp_la {
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u32 size;
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u32 mode;
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u8 data[0];
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};
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struct cudbg_cim_pif_la {
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int size;
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u8 data[0];
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};
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struct cudbg_clk_info {
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u64 retransmit_min;
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u64 retransmit_max;
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u64 persist_timer_min;
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u64 persist_timer_max;
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u64 keepalive_idle_timer;
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u64 keepalive_interval;
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u64 initial_srtt;
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u64 finwait2_timer;
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u32 dack_timer;
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u32 res;
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u32 cclk_ps;
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u32 tre;
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u32 dack_re;
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};
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struct cudbg_tid_info_region {
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u32 ntids;
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u32 nstids;
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u32 stid_base;
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u32 hash_base;
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u32 natids;
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u32 nftids;
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u32 ftid_base;
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u32 aftid_base;
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u32 aftid_end;
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u32 sftid_base;
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u32 nsftids;
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u32 uotid_base;
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u32 nuotids;
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u32 sb;
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u32 flags;
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u32 le_db_conf;
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u32 ip_users;
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u32 ipv6_users;
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u32 hpftid_base;
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u32 nhpftids;
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};
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#define CUDBG_TID_INFO_REV 1
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struct cudbg_tid_info_region_rev1 {
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struct cudbg_ver_hdr ver_hdr;
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struct cudbg_tid_info_region tid;
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u32 tid_start;
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u32 reserved[16];
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};
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#define CUDBG_MAX_FL_QIDS 1024
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struct cudbg_ch_cntxt {
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u32 cntxt_type;
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u32 cntxt_id;
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u32 data[SGE_CTXT_SIZE / 4];
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};
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#define CUDBG_MAX_RPLC_SIZE 128
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struct cudbg_mps_tcam {
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u64 mask;
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u32 rplc[8];
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u32 idx;
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u32 cls_lo;
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u32 cls_hi;
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u32 rplc_size;
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u32 vniy;
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u32 vnix;
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u32 dip_hit;
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u32 vlan_vld;
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u32 repli;
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u16 ivlan;
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u8 addr[ETH_ALEN];
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u8 lookup_type;
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u8 port_num;
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u8 reserved[2];
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};
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#define CUDBG_VPD_PF_SIZE 0x800
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#define CUDBG_SCFG_VER_ADDR 0x06
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#define CUDBG_SCFG_VER_LEN 4
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#define CUDBG_VPD_VER_ADDR 0x18c7
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#define CUDBG_VPD_VER_LEN 2
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struct cudbg_vpd_data {
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u8 sn[SERNUM_LEN + 1];
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u8 bn[PN_LEN + 1];
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u8 na[MACADDR_LEN + 1];
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u8 mn[ID_LEN + 1];
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u16 fw_major;
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u16 fw_minor;
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u16 fw_micro;
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u16 fw_build;
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u32 scfg_vers;
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u32 vpd_vers;
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};
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#define CUDBG_MAX_TCAM_TID 0x800
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enum cudbg_le_entry_types {
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LE_ET_UNKNOWN = 0,
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LE_ET_TCAM_CON = 1,
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LE_ET_TCAM_SERVER = 2,
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LE_ET_TCAM_FILTER = 3,
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LE_ET_TCAM_CLIP = 4,
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LE_ET_TCAM_ROUTING = 5,
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LE_ET_HASH_CON = 6,
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LE_ET_INVALID_TID = 8,
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};
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struct cudbg_tcam {
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u32 filter_start;
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u32 server_start;
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u32 clip_start;
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u32 routing_start;
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u32 tid_hash_base;
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u32 max_tid;
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};
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struct cudbg_tid_data {
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u32 tid;
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u32 dbig_cmd;
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u32 dbig_conf;
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u32 dbig_rsp_stat;
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u32 data[NUM_LE_DB_DBGI_RSP_DATA_INSTANCES];
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};
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#define CUDBG_NUM_ULPTX 11
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#define CUDBG_NUM_ULPTX_READ 512
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struct cudbg_ulptx_la {
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u32 rdptr[CUDBG_NUM_ULPTX];
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u32 wrptr[CUDBG_NUM_ULPTX];
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u32 rddata[CUDBG_NUM_ULPTX];
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u32 rd_data[CUDBG_NUM_ULPTX][CUDBG_NUM_ULPTX_READ];
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};
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#define CUDBG_CHAC_PBT_ADDR 0x2800
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#define CUDBG_CHAC_PBT_LRF 0x3000
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#define CUDBG_CHAC_PBT_DATA 0x3800
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#define CUDBG_PBT_DYNAMIC_ENTRIES 8
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#define CUDBG_PBT_STATIC_ENTRIES 16
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#define CUDBG_LRF_ENTRIES 8
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#define CUDBG_PBT_DATA_ENTRIES 512
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struct cudbg_pbt_tables {
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u32 pbt_dynamic[CUDBG_PBT_DYNAMIC_ENTRIES];
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u32 pbt_static[CUDBG_PBT_STATIC_ENTRIES];
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u32 lrf_table[CUDBG_LRF_ENTRIES];
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u32 pbt_data[CUDBG_PBT_DATA_ENTRIES];
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};
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#define IREG_NUM_ELEM 4
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static const u32 t6_tp_pio_array[][IREG_NUM_ELEM] = {
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{0x7e40, 0x7e44, 0x020, 28}, /* t6_tp_pio_regs_20_to_3b */
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{0x7e40, 0x7e44, 0x040, 10}, /* t6_tp_pio_regs_40_to_49 */
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{0x7e40, 0x7e44, 0x050, 10}, /* t6_tp_pio_regs_50_to_59 */
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{0x7e40, 0x7e44, 0x060, 14}, /* t6_tp_pio_regs_60_to_6d */
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{0x7e40, 0x7e44, 0x06F, 1}, /* t6_tp_pio_regs_6f */
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{0x7e40, 0x7e44, 0x070, 6}, /* t6_tp_pio_regs_70_to_75 */
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{0x7e40, 0x7e44, 0x130, 18}, /* t6_tp_pio_regs_130_to_141 */
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{0x7e40, 0x7e44, 0x145, 19}, /* t6_tp_pio_regs_145_to_157 */
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{0x7e40, 0x7e44, 0x160, 1}, /* t6_tp_pio_regs_160 */
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{0x7e40, 0x7e44, 0x230, 25}, /* t6_tp_pio_regs_230_to_248 */
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{0x7e40, 0x7e44, 0x24a, 3}, /* t6_tp_pio_regs_24c */
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{0x7e40, 0x7e44, 0x8C0, 1} /* t6_tp_pio_regs_8c0 */
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};
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static const u32 t5_tp_pio_array[][IREG_NUM_ELEM] = {
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{0x7e40, 0x7e44, 0x020, 28}, /* t5_tp_pio_regs_20_to_3b */
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{0x7e40, 0x7e44, 0x040, 19}, /* t5_tp_pio_regs_40_to_52 */
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{0x7e40, 0x7e44, 0x054, 2}, /* t5_tp_pio_regs_54_to_55 */
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{0x7e40, 0x7e44, 0x060, 13}, /* t5_tp_pio_regs_60_to_6c */
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{0x7e40, 0x7e44, 0x06F, 1}, /* t5_tp_pio_regs_6f */
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{0x7e40, 0x7e44, 0x120, 4}, /* t5_tp_pio_regs_120_to_123 */
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{0x7e40, 0x7e44, 0x12b, 2}, /* t5_tp_pio_regs_12b_to_12c */
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{0x7e40, 0x7e44, 0x12f, 21}, /* t5_tp_pio_regs_12f_to_143 */
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{0x7e40, 0x7e44, 0x145, 19}, /* t5_tp_pio_regs_145_to_157 */
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{0x7e40, 0x7e44, 0x230, 25}, /* t5_tp_pio_regs_230_to_248 */
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{0x7e40, 0x7e44, 0x8C0, 1} /* t5_tp_pio_regs_8c0 */
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};
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static const u32 t6_tp_tm_pio_array[][IREG_NUM_ELEM] = {
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{0x7e18, 0x7e1c, 0x0, 12}
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};
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static const u32 t5_tp_tm_pio_array[][IREG_NUM_ELEM] = {
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{0x7e18, 0x7e1c, 0x0, 12}
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};
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static const u32 t6_tp_mib_index_array[6][IREG_NUM_ELEM] = {
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{0x7e50, 0x7e54, 0x0, 13},
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{0x7e50, 0x7e54, 0x10, 6},
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{0x7e50, 0x7e54, 0x18, 21},
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{0x7e50, 0x7e54, 0x30, 32},
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{0x7e50, 0x7e54, 0x50, 22},
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{0x7e50, 0x7e54, 0x68, 12}
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};
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static const u32 t5_tp_mib_index_array[9][IREG_NUM_ELEM] = {
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{0x7e50, 0x7e54, 0x0, 13},
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{0x7e50, 0x7e54, 0x10, 6},
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{0x7e50, 0x7e54, 0x18, 8},
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{0x7e50, 0x7e54, 0x20, 13},
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{0x7e50, 0x7e54, 0x30, 16},
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{0x7e50, 0x7e54, 0x40, 16},
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{0x7e50, 0x7e54, 0x50, 16},
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{0x7e50, 0x7e54, 0x60, 6},
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{0x7e50, 0x7e54, 0x68, 4}
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};
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static const u32 t5_sge_dbg_index_array[2][IREG_NUM_ELEM] = {
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{0x10cc, 0x10d0, 0x0, 16},
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{0x10cc, 0x10d4, 0x0, 16},
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};
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static const u32 t5_pcie_pdbg_array[][IREG_NUM_ELEM] = {
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{0x5a04, 0x5a0c, 0x00, 0x20}, /* t5_pcie_pdbg_regs_00_to_20 */
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{0x5a04, 0x5a0c, 0x21, 0x20}, /* t5_pcie_pdbg_regs_21_to_40 */
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{0x5a04, 0x5a0c, 0x41, 0x10}, /* t5_pcie_pdbg_regs_41_to_50 */
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};
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static const u32 t5_pcie_cdbg_array[][IREG_NUM_ELEM] = {
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{0x5a10, 0x5a18, 0x00, 0x20}, /* t5_pcie_cdbg_regs_00_to_20 */
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{0x5a10, 0x5a18, 0x21, 0x18}, /* t5_pcie_cdbg_regs_21_to_37 */
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};
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static const u32 t5_pm_rx_array[][IREG_NUM_ELEM] = {
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{0x8FD0, 0x8FD4, 0x10000, 0x20}, /* t5_pm_rx_regs_10000_to_10020 */
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{0x8FD0, 0x8FD4, 0x10021, 0x0D}, /* t5_pm_rx_regs_10021_to_1002c */
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};
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static const u32 t5_pm_tx_array[][IREG_NUM_ELEM] = {
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{0x8FF0, 0x8FF4, 0x10000, 0x20}, /* t5_pm_tx_regs_10000_to_10020 */
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{0x8FF0, 0x8FF4, 0x10021, 0x1D}, /* t5_pm_tx_regs_10021_to_1003c */
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||
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};
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||
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||
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static const u32 t6_ma_ireg_array[][IREG_NUM_ELEM] = {
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{0x78f8, 0x78fc, 0xa000, 23}, /* t6_ma_regs_a000_to_a016 */
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{0x78f8, 0x78fc, 0xa400, 30}, /* t6_ma_regs_a400_to_a41e */
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{0x78f8, 0x78fc, 0xa800, 20} /* t6_ma_regs_a800_to_a813 */
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||
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};
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||
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||
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static const u32 t6_ma_ireg_array2[][IREG_NUM_ELEM] = {
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||
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{0x78f8, 0x78fc, 0xe400, 17}, /* t6_ma_regs_e400_to_e600 */
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{0x78f8, 0x78fc, 0xe640, 13} /* t6_ma_regs_e640_to_e7c0 */
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||
|
|
};
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||
|
|
|
||
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static const u32 t6_up_cim_reg_array[][IREG_NUM_ELEM] = {
|
||
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{0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
|
||
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{0x7b50, 0x7b54, 0x2080, 0x1d}, /* up_cim_2080_to_20fc */
|
||
|
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{0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
|
||
|
|
{0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
|
||
|
|
{0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
|
||
|
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{0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
|
||
|
|
{0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
|
||
|
|
{0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
|
||
|
|
{0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
|
||
|
|
{0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
|
||
|
|
{0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
|
||
|
|
{0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
|
||
|
|
{0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
static const u32 t5_up_cim_reg_array[][IREG_NUM_ELEM] = {
|
||
|
|
{0x7b50, 0x7b54, 0x2000, 0x20}, /* up_cim_2000_to_207c */
|
||
|
|
{0x7b50, 0x7b54, 0x2080, 0x19}, /* up_cim_2080_to_20ec */
|
||
|
|
{0x7b50, 0x7b54, 0x00, 0x20}, /* up_cim_00_to_7c */
|
||
|
|
{0x7b50, 0x7b54, 0x80, 0x20}, /* up_cim_80_to_fc */
|
||
|
|
{0x7b50, 0x7b54, 0x100, 0x11}, /* up_cim_100_to_14c */
|
||
|
|
{0x7b50, 0x7b54, 0x200, 0x10}, /* up_cim_200_to_23c */
|
||
|
|
{0x7b50, 0x7b54, 0x240, 0x2}, /* up_cim_240_to_244 */
|
||
|
|
{0x7b50, 0x7b54, 0x250, 0x2}, /* up_cim_250_to_254 */
|
||
|
|
{0x7b50, 0x7b54, 0x260, 0x2}, /* up_cim_260_to_264 */
|
||
|
|
{0x7b50, 0x7b54, 0x270, 0x2}, /* up_cim_270_to_274 */
|
||
|
|
{0x7b50, 0x7b54, 0x280, 0x20}, /* up_cim_280_to_2fc */
|
||
|
|
{0x7b50, 0x7b54, 0x300, 0x20}, /* up_cim_300_to_37c */
|
||
|
|
{0x7b50, 0x7b54, 0x380, 0x14}, /* up_cim_380_to_3cc */
|
||
|
|
};
|
||
|
|
|
||
|
|
static const u32 t6_hma_ireg_array[][IREG_NUM_ELEM] = {
|
||
|
|
{0x51320, 0x51324, 0xa000, 32} /* t6_hma_regs_a000_to_a01f */
|
||
|
|
};
|
||
|
|
#endif /* __CUDBG_ENTITY_H__ */
|