447 lines
12 KiB
C
447 lines
12 KiB
C
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/iopoll.h>
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#include <linux/module.h>
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#include <linux/mmc/host.h>
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#include <linux/mmc/mmc.h>
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#include <linux/of.h>
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#include "sdhci-pltfm.h"
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/* HRS - Host Register Set (specific to Cadence) */
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#define SDHCI_CDNS_HRS04 0x10 /* PHY access port */
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#define SDHCI_CDNS_HRS04_ACK BIT(26)
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#define SDHCI_CDNS_HRS04_RD BIT(25)
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#define SDHCI_CDNS_HRS04_WR BIT(24)
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#define SDHCI_CDNS_HRS04_RDATA GENMASK(23, 16)
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#define SDHCI_CDNS_HRS04_WDATA GENMASK(15, 8)
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#define SDHCI_CDNS_HRS04_ADDR GENMASK(5, 0)
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#define SDHCI_CDNS_HRS06 0x18 /* eMMC control */
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#define SDHCI_CDNS_HRS06_TUNE_UP BIT(15)
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#define SDHCI_CDNS_HRS06_TUNE GENMASK(13, 8)
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#define SDHCI_CDNS_HRS06_MODE GENMASK(2, 0)
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#define SDHCI_CDNS_HRS06_MODE_SD 0x0
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#define SDHCI_CDNS_HRS06_MODE_MMC_SDR 0x2
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#define SDHCI_CDNS_HRS06_MODE_MMC_DDR 0x3
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#define SDHCI_CDNS_HRS06_MODE_MMC_HS200 0x4
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#define SDHCI_CDNS_HRS06_MODE_MMC_HS400 0x5
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#define SDHCI_CDNS_HRS06_MODE_MMC_HS400ES 0x6
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/* SRS - Slot Register Set (SDHCI-compatible) */
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#define SDHCI_CDNS_SRS_BASE 0x200
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/* PHY */
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#define SDHCI_CDNS_PHY_DLY_SD_HS 0x00
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#define SDHCI_CDNS_PHY_DLY_SD_DEFAULT 0x01
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR12 0x02
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR25 0x03
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#define SDHCI_CDNS_PHY_DLY_UHS_SDR50 0x04
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#define SDHCI_CDNS_PHY_DLY_UHS_DDR50 0x05
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#define SDHCI_CDNS_PHY_DLY_EMMC_LEGACY 0x06
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#define SDHCI_CDNS_PHY_DLY_EMMC_SDR 0x07
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#define SDHCI_CDNS_PHY_DLY_EMMC_DDR 0x08
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#define SDHCI_CDNS_PHY_DLY_SDCLK 0x0b
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#define SDHCI_CDNS_PHY_DLY_HSMMC 0x0c
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#define SDHCI_CDNS_PHY_DLY_STROBE 0x0d
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/*
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* The tuned val register is 6 bit-wide, but not the whole of the range is
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* available. The range 0-42 seems to be available (then 43 wraps around to 0)
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* but I am not quite sure if it is official. Use only 0 to 39 for safety.
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*/
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#define SDHCI_CDNS_MAX_TUNING_LOOP 40
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struct sdhci_cdns_phy_param {
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u8 addr;
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u8 data;
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};
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struct sdhci_cdns_priv {
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void __iomem *hrs_addr;
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bool enhanced_strobe;
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unsigned int nr_phy_params;
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struct sdhci_cdns_phy_param phy_params[0];
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};
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struct sdhci_cdns_phy_cfg {
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const char *property;
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u8 addr;
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};
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static const struct sdhci_cdns_phy_cfg sdhci_cdns_phy_cfgs[] = {
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{ "cdns,phy-input-delay-sd-highspeed", SDHCI_CDNS_PHY_DLY_SD_HS, },
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{ "cdns,phy-input-delay-legacy", SDHCI_CDNS_PHY_DLY_SD_DEFAULT, },
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{ "cdns,phy-input-delay-sd-uhs-sdr12", SDHCI_CDNS_PHY_DLY_UHS_SDR12, },
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{ "cdns,phy-input-delay-sd-uhs-sdr25", SDHCI_CDNS_PHY_DLY_UHS_SDR25, },
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{ "cdns,phy-input-delay-sd-uhs-sdr50", SDHCI_CDNS_PHY_DLY_UHS_SDR50, },
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{ "cdns,phy-input-delay-sd-uhs-ddr50", SDHCI_CDNS_PHY_DLY_UHS_DDR50, },
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{ "cdns,phy-input-delay-mmc-highspeed", SDHCI_CDNS_PHY_DLY_EMMC_SDR, },
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{ "cdns,phy-input-delay-mmc-ddr", SDHCI_CDNS_PHY_DLY_EMMC_DDR, },
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{ "cdns,phy-dll-delay-sdclk", SDHCI_CDNS_PHY_DLY_SDCLK, },
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{ "cdns,phy-dll-delay-sdclk-hsmmc", SDHCI_CDNS_PHY_DLY_HSMMC, },
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{ "cdns,phy-dll-delay-strobe", SDHCI_CDNS_PHY_DLY_STROBE, },
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};
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static int sdhci_cdns_write_phy_reg(struct sdhci_cdns_priv *priv,
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u8 addr, u8 data)
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{
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void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS04;
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u32 tmp;
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int ret;
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tmp = FIELD_PREP(SDHCI_CDNS_HRS04_WDATA, data) |
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FIELD_PREP(SDHCI_CDNS_HRS04_ADDR, addr);
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writel(tmp, reg);
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tmp |= SDHCI_CDNS_HRS04_WR;
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writel(tmp, reg);
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ret = readl_poll_timeout(reg, tmp, tmp & SDHCI_CDNS_HRS04_ACK, 0, 10);
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if (ret)
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return ret;
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tmp &= ~SDHCI_CDNS_HRS04_WR;
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writel(tmp, reg);
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return 0;
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}
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static unsigned int sdhci_cdns_phy_param_count(struct device_node *np)
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{
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unsigned int count = 0;
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int i;
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for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++)
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if (of_property_read_bool(np, sdhci_cdns_phy_cfgs[i].property))
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count++;
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return count;
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}
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static void sdhci_cdns_phy_param_parse(struct device_node *np,
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struct sdhci_cdns_priv *priv)
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{
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struct sdhci_cdns_phy_param *p = priv->phy_params;
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u32 val;
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int ret, i;
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for (i = 0; i < ARRAY_SIZE(sdhci_cdns_phy_cfgs); i++) {
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ret = of_property_read_u32(np, sdhci_cdns_phy_cfgs[i].property,
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&val);
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if (ret)
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continue;
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p->addr = sdhci_cdns_phy_cfgs[i].addr;
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p->data = val;
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p++;
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}
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}
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static int sdhci_cdns_phy_init(struct sdhci_cdns_priv *priv)
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{
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int ret, i;
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for (i = 0; i < priv->nr_phy_params; i++) {
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ret = sdhci_cdns_write_phy_reg(priv, priv->phy_params[i].addr,
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priv->phy_params[i].data);
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if (ret)
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return ret;
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}
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return 0;
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}
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static inline void *sdhci_cdns_priv(struct sdhci_host *host)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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return sdhci_pltfm_priv(pltfm_host);
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}
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static unsigned int sdhci_cdns_get_timeout_clock(struct sdhci_host *host)
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{
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/*
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* Cadence's spec says the Timeout Clock Frequency is the same as the
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* Base Clock Frequency.
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*/
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return host->max_clk;
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}
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static void sdhci_cdns_set_emmc_mode(struct sdhci_cdns_priv *priv, u32 mode)
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{
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u32 tmp;
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/* The speed mode for eMMC is selected by HRS06 register */
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tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
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tmp &= ~SDHCI_CDNS_HRS06_MODE;
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tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_MODE, mode);
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writel(tmp, priv->hrs_addr + SDHCI_CDNS_HRS06);
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}
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static u32 sdhci_cdns_get_emmc_mode(struct sdhci_cdns_priv *priv)
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{
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u32 tmp;
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tmp = readl(priv->hrs_addr + SDHCI_CDNS_HRS06);
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return FIELD_GET(SDHCI_CDNS_HRS06_MODE, tmp);
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}
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static void sdhci_cdns_set_uhs_signaling(struct sdhci_host *host,
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unsigned int timing)
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{
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struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
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u32 mode;
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switch (timing) {
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case MMC_TIMING_MMC_HS:
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mode = SDHCI_CDNS_HRS06_MODE_MMC_SDR;
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break;
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case MMC_TIMING_MMC_DDR52:
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mode = SDHCI_CDNS_HRS06_MODE_MMC_DDR;
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break;
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case MMC_TIMING_MMC_HS200:
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mode = SDHCI_CDNS_HRS06_MODE_MMC_HS200;
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break;
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case MMC_TIMING_MMC_HS400:
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if (priv->enhanced_strobe)
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mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400ES;
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else
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mode = SDHCI_CDNS_HRS06_MODE_MMC_HS400;
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break;
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default:
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mode = SDHCI_CDNS_HRS06_MODE_SD;
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break;
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}
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sdhci_cdns_set_emmc_mode(priv, mode);
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/* For SD, fall back to the default handler */
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if (mode == SDHCI_CDNS_HRS06_MODE_SD)
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sdhci_set_uhs_signaling(host, timing);
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}
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static const struct sdhci_ops sdhci_cdns_ops = {
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.set_clock = sdhci_set_clock,
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.get_timeout_clock = sdhci_cdns_get_timeout_clock,
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.set_bus_width = sdhci_set_bus_width,
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.reset = sdhci_reset,
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.set_uhs_signaling = sdhci_cdns_set_uhs_signaling,
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};
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static const struct sdhci_pltfm_data sdhci_cdns_pltfm_data = {
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.ops = &sdhci_cdns_ops,
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};
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static int sdhci_cdns_set_tune_val(struct sdhci_host *host, unsigned int val)
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{
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struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
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void __iomem *reg = priv->hrs_addr + SDHCI_CDNS_HRS06;
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u32 tmp;
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if (WARN_ON(!FIELD_FIT(SDHCI_CDNS_HRS06_TUNE, val)))
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return -EINVAL;
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tmp = readl(reg);
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tmp &= ~SDHCI_CDNS_HRS06_TUNE;
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tmp |= FIELD_PREP(SDHCI_CDNS_HRS06_TUNE, val);
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tmp |= SDHCI_CDNS_HRS06_TUNE_UP;
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writel(tmp, reg);
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return readl_poll_timeout(reg, tmp, !(tmp & SDHCI_CDNS_HRS06_TUNE_UP),
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0, 1);
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}
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static int sdhci_cdns_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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int cur_streak = 0;
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int max_streak = 0;
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int end_of_streak = 0;
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int i;
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/*
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* This handler only implements the eMMC tuning that is specific to
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* this controller. Fall back to the standard method for SD timing.
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*/
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if (host->timing != MMC_TIMING_MMC_HS200)
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return sdhci_execute_tuning(mmc, opcode);
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if (WARN_ON(opcode != MMC_SEND_TUNING_BLOCK_HS200))
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return -EINVAL;
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for (i = 0; i < SDHCI_CDNS_MAX_TUNING_LOOP; i++) {
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if (sdhci_cdns_set_tune_val(host, i) ||
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mmc_send_tuning(host->mmc, opcode, NULL)) { /* bad */
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cur_streak = 0;
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} else { /* good */
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cur_streak++;
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if (cur_streak > max_streak) {
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max_streak = cur_streak;
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end_of_streak = i;
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}
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}
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}
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if (!max_streak) {
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dev_err(mmc_dev(host->mmc), "no tuning point found\n");
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return -EIO;
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}
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return sdhci_cdns_set_tune_val(host, end_of_streak - max_streak / 2);
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}
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static void sdhci_cdns_hs400_enhanced_strobe(struct mmc_host *mmc,
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struct mmc_ios *ios)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_cdns_priv *priv = sdhci_cdns_priv(host);
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u32 mode;
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priv->enhanced_strobe = ios->enhanced_strobe;
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mode = sdhci_cdns_get_emmc_mode(priv);
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if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400 && ios->enhanced_strobe)
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sdhci_cdns_set_emmc_mode(priv,
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SDHCI_CDNS_HRS06_MODE_MMC_HS400ES);
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if (mode == SDHCI_CDNS_HRS06_MODE_MMC_HS400ES && !ios->enhanced_strobe)
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sdhci_cdns_set_emmc_mode(priv,
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SDHCI_CDNS_HRS06_MODE_MMC_HS400);
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}
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static int sdhci_cdns_probe(struct platform_device *pdev)
|
||
|
|
{
|
||
|
|
struct sdhci_host *host;
|
||
|
|
struct sdhci_pltfm_host *pltfm_host;
|
||
|
|
struct sdhci_cdns_priv *priv;
|
||
|
|
struct clk *clk;
|
||
|
|
size_t priv_size;
|
||
|
|
unsigned int nr_phy_params;
|
||
|
|
int ret;
|
||
|
|
struct device *dev = &pdev->dev;
|
||
|
|
|
||
|
|
clk = devm_clk_get(dev, NULL);
|
||
|
|
if (IS_ERR(clk))
|
||
|
|
return PTR_ERR(clk);
|
||
|
|
|
||
|
|
ret = clk_prepare_enable(clk);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
nr_phy_params = sdhci_cdns_phy_param_count(dev->of_node);
|
||
|
|
priv_size = sizeof(*priv) + sizeof(priv->phy_params[0]) * nr_phy_params;
|
||
|
|
host = sdhci_pltfm_init(pdev, &sdhci_cdns_pltfm_data, priv_size);
|
||
|
|
if (IS_ERR(host)) {
|
||
|
|
ret = PTR_ERR(host);
|
||
|
|
goto disable_clk;
|
||
|
|
}
|
||
|
|
|
||
|
|
pltfm_host = sdhci_priv(host);
|
||
|
|
pltfm_host->clk = clk;
|
||
|
|
|
||
|
|
priv = sdhci_pltfm_priv(pltfm_host);
|
||
|
|
priv->nr_phy_params = nr_phy_params;
|
||
|
|
priv->hrs_addr = host->ioaddr;
|
||
|
|
priv->enhanced_strobe = false;
|
||
|
|
host->ioaddr += SDHCI_CDNS_SRS_BASE;
|
||
|
|
host->mmc_host_ops.execute_tuning = sdhci_cdns_execute_tuning;
|
||
|
|
host->mmc_host_ops.hs400_enhanced_strobe =
|
||
|
|
sdhci_cdns_hs400_enhanced_strobe;
|
||
|
|
|
||
|
|
sdhci_get_of_property(pdev);
|
||
|
|
|
||
|
|
ret = mmc_of_parse(host->mmc);
|
||
|
|
if (ret)
|
||
|
|
goto free;
|
||
|
|
|
||
|
|
sdhci_cdns_phy_param_parse(dev->of_node, priv);
|
||
|
|
|
||
|
|
ret = sdhci_cdns_phy_init(priv);
|
||
|
|
if (ret)
|
||
|
|
goto free;
|
||
|
|
|
||
|
|
ret = sdhci_add_host(host);
|
||
|
|
if (ret)
|
||
|
|
goto free;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
free:
|
||
|
|
sdhci_pltfm_free(pdev);
|
||
|
|
disable_clk:
|
||
|
|
clk_disable_unprepare(clk);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
#ifdef CONFIG_PM_SLEEP
|
||
|
|
static int sdhci_cdns_resume(struct device *dev)
|
||
|
|
{
|
||
|
|
struct sdhci_host *host = dev_get_drvdata(dev);
|
||
|
|
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
|
||
|
|
struct sdhci_cdns_priv *priv = sdhci_pltfm_priv(pltfm_host);
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = clk_prepare_enable(pltfm_host->clk);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = sdhci_cdns_phy_init(priv);
|
||
|
|
if (ret)
|
||
|
|
goto disable_clk;
|
||
|
|
|
||
|
|
ret = sdhci_resume_host(host);
|
||
|
|
if (ret)
|
||
|
|
goto disable_clk;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
disable_clk:
|
||
|
|
clk_disable_unprepare(pltfm_host->clk);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
#endif
|
||
|
|
|
||
|
|
static const struct dev_pm_ops sdhci_cdns_pm_ops = {
|
||
|
|
SET_SYSTEM_SLEEP_PM_OPS(sdhci_pltfm_suspend, sdhci_cdns_resume)
|
||
|
|
};
|
||
|
|
|
||
|
|
static const struct of_device_id sdhci_cdns_match[] = {
|
||
|
|
{ .compatible = "socionext,uniphier-sd4hc" },
|
||
|
|
{ .compatible = "cdns,sd4hc" },
|
||
|
|
{ /* sentinel */ }
|
||
|
|
};
|
||
|
|
MODULE_DEVICE_TABLE(of, sdhci_cdns_match);
|
||
|
|
|
||
|
|
static struct platform_driver sdhci_cdns_driver = {
|
||
|
|
.driver = {
|
||
|
|
.name = "sdhci-cdns",
|
||
|
|
.pm = &sdhci_cdns_pm_ops,
|
||
|
|
.of_match_table = sdhci_cdns_match,
|
||
|
|
},
|
||
|
|
.probe = sdhci_cdns_probe,
|
||
|
|
.remove = sdhci_pltfm_unregister,
|
||
|
|
};
|
||
|
|
module_platform_driver(sdhci_cdns_driver);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Masahiro Yamada <yamada.masahiro@socionext.com>");
|
||
|
|
MODULE_DESCRIPTION("Cadence SD/SDIO/eMMC Host Controller Driver");
|
||
|
|
MODULE_LICENSE("GPL");
|