396 lines
11 KiB
C
396 lines
11 KiB
C
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/*
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* Synopsys DesignWare I2C adapter driver (slave only).
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*
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* Based on the Synopsys DesignWare I2C adapter driver (master).
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*
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* Copyright (C) 2016 Synopsys Inc.
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*
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* ----------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* ----------------------------------------------------------------------------
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*
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/errno.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include "i2c-designware-core.h"
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static void i2c_dw_configure_fifo_slave(struct dw_i2c_dev *dev)
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{
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/* Configure Tx/Rx FIFO threshold levels. */
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dw_writel(dev, 0, DW_IC_TX_TL);
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dw_writel(dev, 0, DW_IC_RX_TL);
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/* Configure the I2C slave. */
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dw_writel(dev, dev->slave_cfg, DW_IC_CON);
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dw_writel(dev, DW_IC_INTR_SLAVE_MASK, DW_IC_INTR_MASK);
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}
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/**
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* i2c_dw_init_slave() - Initialize the designware i2c slave hardware
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* @dev: device private data
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*
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* This function configures and enables the I2C in slave mode.
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* This function is called during I2C init function, and in case of timeout at
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* run time.
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*/
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static int i2c_dw_init_slave(struct dw_i2c_dev *dev)
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{
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u32 sda_falling_time, scl_falling_time;
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u32 reg, comp_param1;
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u32 hcnt, lcnt;
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int ret;
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ret = i2c_dw_acquire_lock(dev);
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if (ret)
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return ret;
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reg = dw_readl(dev, DW_IC_COMP_TYPE);
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if (reg == ___constant_swab32(DW_IC_COMP_TYPE_VALUE)) {
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/* Configure register endianness access. */
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dev->flags |= ACCESS_SWAP;
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} else if (reg == (DW_IC_COMP_TYPE_VALUE & 0x0000ffff)) {
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/* Configure register access mode 16bit. */
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dev->flags |= ACCESS_16BIT;
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} else if (reg != DW_IC_COMP_TYPE_VALUE) {
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dev_err(dev->dev,
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"Unknown Synopsys component type: 0x%08x\n", reg);
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i2c_dw_release_lock(dev);
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return -ENODEV;
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}
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comp_param1 = dw_readl(dev, DW_IC_COMP_PARAM_1);
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/* Disable the adapter. */
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__i2c_dw_enable_and_wait(dev, false);
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/* Set standard and fast speed deviders for high/low periods. */
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sda_falling_time = dev->sda_falling_time ?: 300; /* ns */
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scl_falling_time = dev->scl_falling_time ?: 300; /* ns */
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/* Set SCL timing parameters for standard-mode. */
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if (dev->ss_hcnt && dev->ss_lcnt) {
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hcnt = dev->ss_hcnt;
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lcnt = dev->ss_lcnt;
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} else {
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hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
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4000, /* tHD;STA = tHIGH = 4.0 us */
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sda_falling_time,
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
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4700, /* tLOW = 4.7 us */
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scl_falling_time,
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0); /* No offset */
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}
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dw_writel(dev, hcnt, DW_IC_SS_SCL_HCNT);
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dw_writel(dev, lcnt, DW_IC_SS_SCL_LCNT);
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dev_dbg(dev->dev, "Standard-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
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/* Set SCL timing parameters for fast-mode or fast-mode plus. */
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if ((dev->clk_freq == 1000000) && dev->fp_hcnt && dev->fp_lcnt) {
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hcnt = dev->fp_hcnt;
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lcnt = dev->fp_lcnt;
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} else if (dev->fs_hcnt && dev->fs_lcnt) {
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hcnt = dev->fs_hcnt;
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lcnt = dev->fs_lcnt;
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} else {
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hcnt = i2c_dw_scl_hcnt(i2c_dw_clk_rate(dev),
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600, /* tHD;STA = tHIGH = 0.6 us */
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sda_falling_time,
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0, /* 0: DW default, 1: Ideal */
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0); /* No offset */
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lcnt = i2c_dw_scl_lcnt(i2c_dw_clk_rate(dev),
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1300, /* tLOW = 1.3 us */
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scl_falling_time,
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0); /* No offset */
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}
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dw_writel(dev, hcnt, DW_IC_FS_SCL_HCNT);
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dw_writel(dev, lcnt, DW_IC_FS_SCL_LCNT);
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dev_dbg(dev->dev, "Fast-mode HCNT:LCNT = %d:%d\n", hcnt, lcnt);
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if ((dev->slave_cfg & DW_IC_CON_SPEED_MASK) ==
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DW_IC_CON_SPEED_HIGH) {
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if ((comp_param1 & DW_IC_COMP_PARAM_1_SPEED_MODE_MASK)
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!= DW_IC_COMP_PARAM_1_SPEED_MODE_HIGH) {
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dev_err(dev->dev, "High Speed not supported!\n");
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dev->slave_cfg &= ~DW_IC_CON_SPEED_MASK;
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dev->slave_cfg |= DW_IC_CON_SPEED_FAST;
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} else if (dev->hs_hcnt && dev->hs_lcnt) {
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hcnt = dev->hs_hcnt;
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lcnt = dev->hs_lcnt;
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dw_writel(dev, hcnt, DW_IC_HS_SCL_HCNT);
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dw_writel(dev, lcnt, DW_IC_HS_SCL_LCNT);
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dev_dbg(dev->dev, "HighSpeed-mode HCNT:LCNT = %d:%d\n",
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hcnt, lcnt);
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}
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}
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/* Configure SDA Hold Time if required. */
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reg = dw_readl(dev, DW_IC_COMP_VERSION);
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if (reg >= DW_IC_SDA_HOLD_MIN_VERS) {
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if (!dev->sda_hold_time) {
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/* Keep previous hold time setting if no one set it. */
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dev->sda_hold_time = dw_readl(dev, DW_IC_SDA_HOLD);
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}
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/*
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* Workaround for avoiding TX arbitration lost in case I2C
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* slave pulls SDA down "too quickly" after falling egde of
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* SCL by enabling non-zero SDA RX hold. Specification says it
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* extends incoming SDA low to high transition while SCL is
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* high but it apprears to help also above issue.
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*/
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if (!(dev->sda_hold_time & DW_IC_SDA_HOLD_RX_MASK))
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dev->sda_hold_time |= 1 << DW_IC_SDA_HOLD_RX_SHIFT;
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dw_writel(dev, dev->sda_hold_time, DW_IC_SDA_HOLD);
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} else {
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dev_warn(dev->dev,
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"Hardware too old to adjust SDA hold time.\n");
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}
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i2c_dw_configure_fifo_slave(dev);
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i2c_dw_release_lock(dev);
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return 0;
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}
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static int i2c_dw_reg_slave(struct i2c_client *slave)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter);
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if (dev->slave)
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return -EBUSY;
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if (slave->flags & I2C_CLIENT_TEN)
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return -EAFNOSUPPORT;
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pm_runtime_get_sync(dev->dev);
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/*
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* Set slave address in the IC_SAR register,
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* the address to which the DW_apb_i2c responds.
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*/
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__i2c_dw_enable(dev, false);
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dw_writel(dev, slave->addr, DW_IC_SAR);
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dev->slave = slave;
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__i2c_dw_enable(dev, true);
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dev->cmd_err = 0;
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dev->msg_write_idx = 0;
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dev->msg_read_idx = 0;
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dev->msg_err = 0;
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dev->status = STATUS_IDLE;
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dev->abort_source = 0;
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dev->rx_outstanding = 0;
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return 0;
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}
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static int i2c_dw_unreg_slave(struct i2c_client *slave)
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{
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struct dw_i2c_dev *dev = i2c_get_adapdata(slave->adapter);
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dev->disable_int(dev);
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dev->disable(dev);
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dev->slave = NULL;
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pm_runtime_put(dev->dev);
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return 0;
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}
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static u32 i2c_dw_read_clear_intrbits_slave(struct dw_i2c_dev *dev)
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{
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u32 stat;
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/*
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* The IC_INTR_STAT register just indicates "enabled" interrupts.
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* Ths unmasked raw version of interrupt status bits are available
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* in the IC_RAW_INTR_STAT register.
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*
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* That is,
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* stat = dw_readl(IC_INTR_STAT);
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* equals to,
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* stat = dw_readl(IC_RAW_INTR_STAT) & dw_readl(IC_INTR_MASK);
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*
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* The raw version might be useful for debugging purposes.
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*/
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stat = dw_readl(dev, DW_IC_INTR_STAT);
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/*
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* Do not use the IC_CLR_INTR register to clear interrupts, or
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* you'll miss some interrupts, triggered during the period from
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* dw_readl(IC_INTR_STAT) to dw_readl(IC_CLR_INTR).
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*
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* Instead, use the separately-prepared IC_CLR_* registers.
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*/
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if (stat & DW_IC_INTR_TX_ABRT)
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dw_readl(dev, DW_IC_CLR_TX_ABRT);
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if (stat & DW_IC_INTR_RX_UNDER)
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dw_readl(dev, DW_IC_CLR_RX_UNDER);
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if (stat & DW_IC_INTR_RX_OVER)
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dw_readl(dev, DW_IC_CLR_RX_OVER);
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if (stat & DW_IC_INTR_TX_OVER)
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dw_readl(dev, DW_IC_CLR_TX_OVER);
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if (stat & DW_IC_INTR_RX_DONE)
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dw_readl(dev, DW_IC_CLR_RX_DONE);
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if (stat & DW_IC_INTR_ACTIVITY)
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dw_readl(dev, DW_IC_CLR_ACTIVITY);
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if (stat & DW_IC_INTR_STOP_DET)
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dw_readl(dev, DW_IC_CLR_STOP_DET);
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if (stat & DW_IC_INTR_START_DET)
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dw_readl(dev, DW_IC_CLR_START_DET);
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if (stat & DW_IC_INTR_GEN_CALL)
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dw_readl(dev, DW_IC_CLR_GEN_CALL);
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return stat;
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}
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/*
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* Interrupt service routine. This gets called whenever an I2C slave interrupt
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* occurs.
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*/
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static int i2c_dw_irq_handler_slave(struct dw_i2c_dev *dev)
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{
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u32 raw_stat, stat, enabled;
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u8 val, slave_activity;
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stat = dw_readl(dev, DW_IC_INTR_STAT);
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enabled = dw_readl(dev, DW_IC_ENABLE);
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raw_stat = dw_readl(dev, DW_IC_RAW_INTR_STAT);
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slave_activity = ((dw_readl(dev, DW_IC_STATUS) &
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DW_IC_STATUS_SLAVE_ACTIVITY) >> 6);
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if (!enabled || !(raw_stat & ~DW_IC_INTR_ACTIVITY) || !dev->slave)
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return 0;
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dev_dbg(dev->dev,
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"%#x STATUS SLAVE_ACTIVITY=%#x : RAW_INTR_STAT=%#x : INTR_STAT=%#x\n",
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enabled, slave_activity, raw_stat, stat);
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if ((stat & DW_IC_INTR_RX_FULL) && (stat & DW_IC_INTR_STOP_DET))
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i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_REQUESTED, &val);
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if (stat & DW_IC_INTR_RD_REQ) {
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if (slave_activity) {
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if (stat & DW_IC_INTR_RX_FULL) {
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val = dw_readl(dev, DW_IC_DATA_CMD);
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if (!i2c_slave_event(dev->slave,
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I2C_SLAVE_WRITE_RECEIVED,
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&val)) {
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dev_vdbg(dev->dev, "Byte %X acked!",
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val);
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}
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dw_readl(dev, DW_IC_CLR_RD_REQ);
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stat = i2c_dw_read_clear_intrbits_slave(dev);
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} else {
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dw_readl(dev, DW_IC_CLR_RD_REQ);
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dw_readl(dev, DW_IC_CLR_RX_UNDER);
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stat = i2c_dw_read_clear_intrbits_slave(dev);
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}
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if (!i2c_slave_event(dev->slave,
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I2C_SLAVE_READ_REQUESTED,
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&val))
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dw_writel(dev, val, DW_IC_DATA_CMD);
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}
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}
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if (stat & DW_IC_INTR_RX_DONE) {
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if (!i2c_slave_event(dev->slave, I2C_SLAVE_READ_PROCESSED,
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&val))
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dw_readl(dev, DW_IC_CLR_RX_DONE);
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i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val);
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stat = i2c_dw_read_clear_intrbits_slave(dev);
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return 1;
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}
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if (stat & DW_IC_INTR_RX_FULL) {
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val = dw_readl(dev, DW_IC_DATA_CMD);
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if (!i2c_slave_event(dev->slave, I2C_SLAVE_WRITE_RECEIVED,
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&val))
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dev_vdbg(dev->dev, "Byte %X acked!", val);
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} else {
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i2c_slave_event(dev->slave, I2C_SLAVE_STOP, &val);
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stat = i2c_dw_read_clear_intrbits_slave(dev);
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}
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return 1;
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}
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||
|
|
static irqreturn_t i2c_dw_isr_slave(int this_irq, void *dev_id)
|
||
|
|
{
|
||
|
|
struct dw_i2c_dev *dev = dev_id;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
i2c_dw_read_clear_intrbits_slave(dev);
|
||
|
|
ret = i2c_dw_irq_handler_slave(dev);
|
||
|
|
if (ret > 0)
|
||
|
|
complete(&dev->cmd_complete);
|
||
|
|
|
||
|
|
return IRQ_RETVAL(ret);
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct i2c_algorithm i2c_dw_algo = {
|
||
|
|
.functionality = i2c_dw_func,
|
||
|
|
.reg_slave = i2c_dw_reg_slave,
|
||
|
|
.unreg_slave = i2c_dw_unreg_slave,
|
||
|
|
};
|
||
|
|
|
||
|
|
int i2c_dw_probe_slave(struct dw_i2c_dev *dev)
|
||
|
|
{
|
||
|
|
struct i2c_adapter *adap = &dev->adapter;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
init_completion(&dev->cmd_complete);
|
||
|
|
|
||
|
|
dev->init = i2c_dw_init_slave;
|
||
|
|
dev->disable = i2c_dw_disable;
|
||
|
|
dev->disable_int = i2c_dw_disable_int;
|
||
|
|
|
||
|
|
ret = dev->init(dev);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
snprintf(adap->name, sizeof(adap->name),
|
||
|
|
"Synopsys DesignWare I2C Slave adapter");
|
||
|
|
adap->retries = 3;
|
||
|
|
adap->algo = &i2c_dw_algo;
|
||
|
|
adap->dev.parent = dev->dev;
|
||
|
|
i2c_set_adapdata(adap, dev);
|
||
|
|
|
||
|
|
ret = devm_request_irq(dev->dev, dev->irq, i2c_dw_isr_slave,
|
||
|
|
IRQF_SHARED, dev_name(dev->dev), dev);
|
||
|
|
if (ret) {
|
||
|
|
dev_err(dev->dev, "failure requesting irq %i: %d\n",
|
||
|
|
dev->irq, ret);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
ret = i2c_add_numbered_adapter(adap);
|
||
|
|
if (ret)
|
||
|
|
dev_err(dev->dev, "failure adding adapter: %d\n", ret);
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL_GPL(i2c_dw_probe_slave);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("Luis Oliveira <lolivei@synopsys.com>");
|
||
|
|
MODULE_DESCRIPTION("Synopsys DesignWare I2C bus slave adapter");
|
||
|
|
MODULE_LICENSE("GPL v2");
|