266 lines
8.0 KiB
C
266 lines
8.0 KiB
C
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/*
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* Copyright 2013 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alon Levy
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*/
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#include "qxl_drv.h"
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#include "qxl_object.h"
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#include <drm/drm_crtc_helper.h>
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#include <linux/io-mapping.h>
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int qxl_log_level;
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static bool qxl_check_device(struct qxl_device *qdev)
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{
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struct qxl_rom *rom = qdev->rom;
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if (rom->magic != 0x4f525851) {
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DRM_ERROR("bad rom signature %x\n", rom->magic);
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return false;
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}
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DRM_INFO("Device Version %d.%d\n", rom->id, rom->update_id);
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DRM_INFO("Compression level %d log level %d\n", rom->compression_level,
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rom->log_level);
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DRM_INFO("%d io pages at offset 0x%x\n",
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rom->num_io_pages, rom->pages_offset);
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DRM_INFO("%d byte draw area at offset 0x%x\n",
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rom->surface0_area_size, rom->draw_area_offset);
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qdev->vram_size = rom->surface0_area_size;
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DRM_INFO("RAM header offset: 0x%x\n", rom->ram_header_offset);
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return true;
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}
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static void setup_hw_slot(struct qxl_device *qdev, int slot_index,
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struct qxl_memslot *slot)
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{
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qdev->ram_header->mem_slot.mem_start = slot->start_phys_addr;
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qdev->ram_header->mem_slot.mem_end = slot->end_phys_addr;
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qxl_io_memslot_add(qdev, slot_index);
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}
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static uint8_t setup_slot(struct qxl_device *qdev, uint8_t slot_index_offset,
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unsigned long start_phys_addr, unsigned long end_phys_addr)
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{
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uint64_t high_bits;
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struct qxl_memslot *slot;
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uint8_t slot_index;
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slot_index = qdev->rom->slots_start + slot_index_offset;
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slot = &qdev->mem_slots[slot_index];
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slot->start_phys_addr = start_phys_addr;
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slot->end_phys_addr = end_phys_addr;
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setup_hw_slot(qdev, slot_index, slot);
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slot->generation = qdev->rom->slot_generation;
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high_bits = slot_index << qdev->slot_gen_bits;
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high_bits |= slot->generation;
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high_bits <<= (64 - (qdev->slot_gen_bits + qdev->slot_id_bits));
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slot->high_bits = high_bits;
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return slot_index;
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}
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void qxl_reinit_memslots(struct qxl_device *qdev)
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{
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setup_hw_slot(qdev, qdev->main_mem_slot, &qdev->mem_slots[qdev->main_mem_slot]);
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setup_hw_slot(qdev, qdev->surfaces_mem_slot, &qdev->mem_slots[qdev->surfaces_mem_slot]);
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}
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static void qxl_gc_work(struct work_struct *work)
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{
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struct qxl_device *qdev = container_of(work, struct qxl_device, gc_work);
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qxl_garbage_collect(qdev);
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}
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int qxl_device_init(struct qxl_device *qdev,
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struct drm_driver *drv,
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struct pci_dev *pdev)
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{
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int r, sb;
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r = drm_dev_init(&qdev->ddev, drv, &pdev->dev);
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if (r)
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return r;
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qdev->ddev.pdev = pdev;
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pci_set_drvdata(pdev, &qdev->ddev);
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qdev->ddev.dev_private = qdev;
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mutex_init(&qdev->gem.mutex);
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mutex_init(&qdev->update_area_mutex);
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mutex_init(&qdev->release_mutex);
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mutex_init(&qdev->surf_evict_mutex);
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qxl_gem_init(qdev);
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qdev->rom_base = pci_resource_start(pdev, 2);
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qdev->rom_size = pci_resource_len(pdev, 2);
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qdev->vram_base = pci_resource_start(pdev, 0);
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qdev->io_base = pci_resource_start(pdev, 3);
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qdev->vram_mapping = io_mapping_create_wc(qdev->vram_base, pci_resource_len(pdev, 0));
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if (pci_resource_len(pdev, 4) > 0) {
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/* 64bit surface bar present */
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sb = 4;
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qdev->surfaceram_base = pci_resource_start(pdev, sb);
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qdev->surfaceram_size = pci_resource_len(pdev, sb);
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qdev->surface_mapping =
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io_mapping_create_wc(qdev->surfaceram_base,
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qdev->surfaceram_size);
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}
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if (qdev->surface_mapping == NULL) {
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/* 64bit surface bar not present (or mapping failed) */
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sb = 1;
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qdev->surfaceram_base = pci_resource_start(pdev, sb);
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qdev->surfaceram_size = pci_resource_len(pdev, sb);
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qdev->surface_mapping =
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io_mapping_create_wc(qdev->surfaceram_base,
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qdev->surfaceram_size);
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}
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DRM_DEBUG_KMS("qxl: vram %llx-%llx(%dM %dk), surface %llx-%llx(%dM %dk, %s)\n",
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(unsigned long long)qdev->vram_base,
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(unsigned long long)pci_resource_end(pdev, 0),
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(int)pci_resource_len(pdev, 0) / 1024 / 1024,
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(int)pci_resource_len(pdev, 0) / 1024,
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(unsigned long long)qdev->surfaceram_base,
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(unsigned long long)pci_resource_end(pdev, sb),
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(int)qdev->surfaceram_size / 1024 / 1024,
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(int)qdev->surfaceram_size / 1024,
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(sb == 4) ? "64bit" : "32bit");
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qdev->rom = ioremap(qdev->rom_base, qdev->rom_size);
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if (!qdev->rom) {
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pr_err("Unable to ioremap ROM\n");
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return -ENOMEM;
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}
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qxl_check_device(qdev);
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r = qxl_bo_init(qdev);
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if (r) {
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DRM_ERROR("bo init failed %d\n", r);
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return r;
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}
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qdev->ram_header = ioremap(qdev->vram_base +
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qdev->rom->ram_header_offset,
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sizeof(*qdev->ram_header));
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qdev->command_ring = qxl_ring_create(&(qdev->ram_header->cmd_ring_hdr),
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sizeof(struct qxl_command),
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QXL_COMMAND_RING_SIZE,
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qdev->io_base + QXL_IO_NOTIFY_CMD,
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false,
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&qdev->display_event);
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qdev->cursor_ring = qxl_ring_create(
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&(qdev->ram_header->cursor_ring_hdr),
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sizeof(struct qxl_command),
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QXL_CURSOR_RING_SIZE,
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qdev->io_base + QXL_IO_NOTIFY_CMD,
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false,
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&qdev->cursor_event);
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qdev->release_ring = qxl_ring_create(
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&(qdev->ram_header->release_ring_hdr),
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sizeof(uint64_t),
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QXL_RELEASE_RING_SIZE, 0, true,
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NULL);
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/* TODO - slot initialization should happen on reset. where is our
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* reset handler? */
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qdev->n_mem_slots = qdev->rom->slots_end;
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qdev->slot_gen_bits = qdev->rom->slot_gen_bits;
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qdev->slot_id_bits = qdev->rom->slot_id_bits;
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qdev->va_slot_mask =
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(~(uint64_t)0) >> (qdev->slot_id_bits + qdev->slot_gen_bits);
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qdev->mem_slots =
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kmalloc(qdev->n_mem_slots * sizeof(struct qxl_memslot),
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GFP_KERNEL);
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idr_init(&qdev->release_idr);
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spin_lock_init(&qdev->release_idr_lock);
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spin_lock_init(&qdev->release_lock);
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idr_init(&qdev->surf_id_idr);
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spin_lock_init(&qdev->surf_id_idr_lock);
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mutex_init(&qdev->async_io_mutex);
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/* reset the device into a known state - no memslots, no primary
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* created, no surfaces. */
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qxl_io_reset(qdev);
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/* must initialize irq before first async io - slot creation */
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r = qxl_irq_init(qdev);
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if (r)
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return r;
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/*
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* Note that virtual is surface0. We rely on the single ioremap done
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* before.
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*/
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qdev->main_mem_slot = setup_slot(qdev, 0,
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(unsigned long)qdev->vram_base,
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(unsigned long)qdev->vram_base + qdev->rom->ram_header_offset);
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qdev->surfaces_mem_slot = setup_slot(qdev, 1,
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(unsigned long)qdev->surfaceram_base,
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(unsigned long)qdev->surfaceram_base + qdev->surfaceram_size);
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DRM_INFO("main mem slot %d [%lx,%x]\n",
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qdev->main_mem_slot,
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(unsigned long)qdev->vram_base, qdev->rom->ram_header_offset);
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DRM_INFO("surface mem slot %d [%lx,%lx]\n",
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qdev->surfaces_mem_slot,
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(unsigned long)qdev->surfaceram_base,
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(unsigned long)qdev->surfaceram_size);
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INIT_WORK(&qdev->gc_work, qxl_gc_work);
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return 0;
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}
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void qxl_device_fini(struct qxl_device *qdev)
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{
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if (qdev->current_release_bo[0])
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qxl_bo_unref(&qdev->current_release_bo[0]);
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if (qdev->current_release_bo[1])
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qxl_bo_unref(&qdev->current_release_bo[1]);
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flush_work(&qdev->gc_work);
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qxl_ring_free(qdev->command_ring);
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qxl_ring_free(qdev->cursor_ring);
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qxl_ring_free(qdev->release_ring);
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qxl_gem_fini(qdev);
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qxl_bo_fini(qdev);
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io_mapping_free(qdev->surface_mapping);
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io_mapping_free(qdev->vram_mapping);
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iounmap(qdev->ram_header);
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iounmap(qdev->rom);
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qdev->rom = NULL;
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}
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