94 lines
3.0 KiB
C
94 lines
3.0 KiB
C
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/*
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* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include "acr.h"
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#include "gm200.h"
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#define TEGRA186_MC_BASE 0x02c10000
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static int
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gp10b_secboot_oneinit(struct nvkm_secboot *sb)
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{
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struct gm200_secboot *gsb = gm200_secboot(sb);
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int ret;
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ret = gm20b_secboot_tegra_read_wpr(gsb, TEGRA186_MC_BASE);
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if (ret)
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return ret;
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return gm200_secboot_oneinit(sb);
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}
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static const struct nvkm_secboot_func
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gp10b_secboot = {
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.dtor = gm200_secboot_dtor,
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.oneinit = gp10b_secboot_oneinit,
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.fini = gm200_secboot_fini,
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.run_blob = gm200_secboot_run_blob,
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};
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int
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gp10b_secboot_new(struct nvkm_device *device, int index,
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struct nvkm_secboot **psb)
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{
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int ret;
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struct gm200_secboot *gsb;
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struct nvkm_acr *acr;
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acr = acr_r352_new(BIT(NVKM_SECBOOT_FALCON_FECS) |
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BIT(NVKM_SECBOOT_FALCON_GPCCS) |
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BIT(NVKM_SECBOOT_FALCON_PMU));
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if (IS_ERR(acr))
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return PTR_ERR(acr);
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gsb = kzalloc(sizeof(*gsb), GFP_KERNEL);
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if (!gsb) {
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psb = NULL;
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return -ENOMEM;
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}
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*psb = &gsb->base;
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ret = nvkm_secboot_ctor(&gp10b_secboot, acr, device, index, &gsb->base);
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if (ret)
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return ret;
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return 0;
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}
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MODULE_FIRMWARE("nvidia/gp10b/acr/bl.bin");
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MODULE_FIRMWARE("nvidia/gp10b/acr/ucode_load.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_data.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/fecs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_bl.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_inst.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_data.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/gpccs_sig.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/sw_ctx.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/sw_nonctx.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/sw_bundle_init.bin");
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MODULE_FIRMWARE("nvidia/gp10b/gr/sw_method_init.bin");
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MODULE_FIRMWARE("nvidia/gp10b/pmu/desc.bin");
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MODULE_FIRMWARE("nvidia/gp10b/pmu/image.bin");
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MODULE_FIRMWARE("nvidia/gp10b/pmu/sig.bin");
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