467 lines
13 KiB
C
467 lines
13 KiB
C
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/*
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* Copyright (C) 2010 Francisco Jerez.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "nv04.h"
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#include "fbmem.h"
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#include <subdev/bios.h>
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#include <subdev/bios/init.h>
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#include <subdev/bios/pll.h>
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#include <subdev/clk/pll.h>
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#include <subdev/vga.h>
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static void
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nv04_devinit_meminit(struct nvkm_devinit *init)
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{
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struct nvkm_subdev *subdev = &init->subdev;
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struct nvkm_device *device = subdev->device;
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u32 patt = 0xdeadbeef;
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struct io_mapping *fb;
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int i;
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/* Map the framebuffer aperture */
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fb = fbmem_init(device);
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if (!fb) {
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nvkm_error(subdev, "failed to map fb\n");
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return;
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}
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/* Sequencer and refresh off */
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nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) | 0x20);
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nvkm_mask(device, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
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nvkm_mask(device, NV04_PFB_BOOT_0, ~0,
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NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
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NV04_PFB_BOOT_0_RAM_WIDTH_128 |
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NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
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for (i = 0; i < 4; i++)
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fbmem_poke(fb, 4 * i, patt);
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fbmem_poke(fb, 0x400000, patt + 1);
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if (fbmem_peek(fb, 0) == patt + 1) {
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nvkm_mask(device, NV04_PFB_BOOT_0,
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NV04_PFB_BOOT_0_RAM_TYPE,
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NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
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nvkm_mask(device, NV04_PFB_DEBUG_0,
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NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
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for (i = 0; i < 4; i++)
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fbmem_poke(fb, 4 * i, patt);
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if ((fbmem_peek(fb, 0xc) & 0xffff) != (patt & 0xffff))
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nvkm_mask(device, NV04_PFB_BOOT_0,
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NV04_PFB_BOOT_0_RAM_WIDTH_128 |
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NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
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} else
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if ((fbmem_peek(fb, 0xc) & 0xffff0000) != (patt & 0xffff0000)) {
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nvkm_mask(device, NV04_PFB_BOOT_0,
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NV04_PFB_BOOT_0_RAM_WIDTH_128 |
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NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
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} else
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if (fbmem_peek(fb, 0) != patt) {
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if (fbmem_readback(fb, 0x800000, patt))
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nvkm_mask(device, NV04_PFB_BOOT_0,
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NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
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else
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nvkm_mask(device, NV04_PFB_BOOT_0,
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NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
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nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
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NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
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} else
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if (!fbmem_readback(fb, 0x800000, patt)) {
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nvkm_mask(device, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
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}
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/* Refresh on, sequencer on */
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nvkm_mask(device, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
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nvkm_wrvgas(device, 0, 1, nvkm_rdvgas(device, 0, 1) & ~0x20);
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fbmem_fini(fb);
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}
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static int
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powerctrl_1_shift(int chip_version, int reg)
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{
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int shift = -4;
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if (chip_version < 0x17 || chip_version == 0x1a || chip_version == 0x20)
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return shift;
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switch (reg) {
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case 0x680520:
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shift += 4; /* fall through */
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case 0x680508:
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shift += 4; /* fall through */
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case 0x680504:
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shift += 4; /* fall through */
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case 0x680500:
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shift += 4;
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}
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/*
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* the shift for vpll regs is only used for nv3x chips with a single
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* stage pll
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*/
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if (shift > 4 && (chip_version < 0x32 || chip_version == 0x35 ||
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chip_version == 0x36 || chip_version >= 0x40))
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shift = -4;
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return shift;
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}
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void
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setPLL_single(struct nvkm_devinit *init, u32 reg,
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struct nvkm_pll_vals *pv)
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{
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struct nvkm_device *device = init->subdev.device;
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int chip_version = device->bios->version.chip;
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uint32_t oldpll = nvkm_rd32(device, reg);
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int oldN = (oldpll >> 8) & 0xff, oldM = oldpll & 0xff;
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uint32_t pll = (oldpll & 0xfff80000) | pv->log2P << 16 | pv->NM1;
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uint32_t saved_powerctrl_1 = 0;
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int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg);
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if (oldpll == pll)
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return; /* already set */
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if (shift_powerctrl_1 >= 0) {
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saved_powerctrl_1 = nvkm_rd32(device, 0x001584);
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nvkm_wr32(device, 0x001584,
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(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
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1 << shift_powerctrl_1);
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}
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if (oldM && pv->M1 && (oldN / oldM < pv->N1 / pv->M1))
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/* upclock -- write new post divider first */
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nvkm_wr32(device, reg, pv->log2P << 16 | (oldpll & 0xffff));
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else
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/* downclock -- write new NM first */
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nvkm_wr32(device, reg, (oldpll & 0xffff0000) | pv->NM1);
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if ((chip_version < 0x17 || chip_version == 0x1a) &&
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chip_version != 0x11)
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/* wait a bit on older chips */
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msleep(64);
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nvkm_rd32(device, reg);
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/* then write the other half as well */
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nvkm_wr32(device, reg, pll);
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if (shift_powerctrl_1 >= 0)
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nvkm_wr32(device, 0x001584, saved_powerctrl_1);
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}
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static uint32_t
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new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580)
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{
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bool head_a = (reg1 == 0x680508);
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if (ss) /* single stage pll mode */
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ramdac580 |= head_a ? 0x00000100 : 0x10000000;
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else
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ramdac580 &= head_a ? 0xfffffeff : 0xefffffff;
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return ramdac580;
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}
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void
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setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1,
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struct nvkm_pll_vals *pv)
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{
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struct nvkm_device *device = init->subdev.device;
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int chip_version = device->bios->version.chip;
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bool nv3035 = chip_version == 0x30 || chip_version == 0x35;
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uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70);
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uint32_t oldpll1 = nvkm_rd32(device, reg1);
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uint32_t oldpll2 = !nv3035 ? nvkm_rd32(device, reg2) : 0;
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uint32_t pll1 = (oldpll1 & 0xfff80000) | pv->log2P << 16 | pv->NM1;
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uint32_t pll2 = (oldpll2 & 0x7fff0000) | 1 << 31 | pv->NM2;
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uint32_t oldramdac580 = 0, ramdac580 = 0;
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bool single_stage = !pv->NM2 || pv->N2 == pv->M2; /* nv41+ only */
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uint32_t saved_powerctrl_1 = 0, savedc040 = 0;
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int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1);
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/* model specific additions to generic pll1 and pll2 set up above */
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if (nv3035) {
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pll1 = (pll1 & 0xfcc7ffff) | (pv->N2 & 0x18) << 21 |
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(pv->N2 & 0x7) << 19 | 8 << 4 | (pv->M2 & 7) << 4;
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pll2 = 0;
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}
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if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */
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oldramdac580 = nvkm_rd32(device, 0x680580);
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ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580);
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if (oldramdac580 != ramdac580)
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oldpll1 = ~0; /* force mismatch */
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if (single_stage)
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/* magic value used by nvidia in single stage mode */
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pll2 |= 0x011f;
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}
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if (chip_version > 0x70)
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/* magic bits set by the blob (but not the bios) on g71-73 */
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pll1 = (pll1 & 0x7fffffff) | (single_stage ? 0x4 : 0xc) << 28;
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if (oldpll1 == pll1 && oldpll2 == pll2)
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return; /* already set */
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if (shift_powerctrl_1 >= 0) {
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saved_powerctrl_1 = nvkm_rd32(device, 0x001584);
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nvkm_wr32(device, 0x001584,
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(saved_powerctrl_1 & ~(0xf << shift_powerctrl_1)) |
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1 << shift_powerctrl_1);
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}
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if (chip_version >= 0x40) {
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int shift_c040 = 14;
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switch (reg1) {
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case 0x680504:
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shift_c040 += 2; /* fall through */
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case 0x680500:
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shift_c040 += 2; /* fall through */
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case 0x680520:
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shift_c040 += 2; /* fall through */
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case 0x680508:
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shift_c040 += 2;
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}
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savedc040 = nvkm_rd32(device, 0xc040);
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if (shift_c040 != 14)
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nvkm_wr32(device, 0xc040, savedc040 & ~(3 << shift_c040));
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}
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if (oldramdac580 != ramdac580)
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nvkm_wr32(device, 0x680580, ramdac580);
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if (!nv3035)
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nvkm_wr32(device, reg2, pll2);
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nvkm_wr32(device, reg1, pll1);
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if (shift_powerctrl_1 >= 0)
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nvkm_wr32(device, 0x001584, saved_powerctrl_1);
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if (chip_version >= 0x40)
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nvkm_wr32(device, 0xc040, savedc040);
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}
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void
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setPLL_double_lowregs(struct nvkm_devinit *init, u32 NMNMreg,
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struct nvkm_pll_vals *pv)
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{
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/* When setting PLLs, there is a merry game of disabling and enabling
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* various bits of hardware during the process. This function is a
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* synthesis of six nv4x traces, nearly each card doing a subtly
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* different thing. With luck all the necessary bits for each card are
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* combined herein. Without luck it deviates from each card's formula
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* so as to not work on any :)
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*/
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struct nvkm_device *device = init->subdev.device;
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uint32_t Preg = NMNMreg - 4;
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bool mpll = Preg == 0x4020;
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uint32_t oldPval = nvkm_rd32(device, Preg);
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uint32_t NMNM = pv->NM2 << 16 | pv->NM1;
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uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) |
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0xc << 28 | pv->log2P << 16;
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uint32_t saved4600 = 0;
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/* some cards have different maskc040s */
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uint32_t maskc040 = ~(3 << 14), savedc040;
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bool single_stage = !pv->NM2 || pv->N2 == pv->M2;
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if (nvkm_rd32(device, NMNMreg) == NMNM && (oldPval & 0xc0070000) == Pval)
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return;
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if (Preg == 0x4000)
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maskc040 = ~0x333;
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if (Preg == 0x4058)
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maskc040 = ~(0xc << 24);
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if (mpll) {
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struct nvbios_pll info;
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uint8_t Pval2;
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if (nvbios_pll_parse(device->bios, Preg, &info))
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return;
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Pval2 = pv->log2P + info.bias_p;
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if (Pval2 > info.max_p)
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Pval2 = info.max_p;
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Pval |= 1 << 28 | Pval2 << 20;
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saved4600 = nvkm_rd32(device, 0x4600);
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nvkm_wr32(device, 0x4600, saved4600 | 8 << 28);
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}
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if (single_stage)
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Pval |= mpll ? 1 << 12 : 1 << 8;
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nvkm_wr32(device, Preg, oldPval | 1 << 28);
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nvkm_wr32(device, Preg, Pval & ~(4 << 28));
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if (mpll) {
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Pval |= 8 << 20;
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nvkm_wr32(device, 0x4020, Pval & ~(0xc << 28));
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nvkm_wr32(device, 0x4038, Pval & ~(0xc << 28));
|
||
|
|
}
|
||
|
|
|
||
|
|
savedc040 = nvkm_rd32(device, 0xc040);
|
||
|
|
nvkm_wr32(device, 0xc040, savedc040 & maskc040);
|
||
|
|
|
||
|
|
nvkm_wr32(device, NMNMreg, NMNM);
|
||
|
|
if (NMNMreg == 0x4024)
|
||
|
|
nvkm_wr32(device, 0x403c, NMNM);
|
||
|
|
|
||
|
|
nvkm_wr32(device, Preg, Pval);
|
||
|
|
if (mpll) {
|
||
|
|
Pval &= ~(8 << 20);
|
||
|
|
nvkm_wr32(device, 0x4020, Pval);
|
||
|
|
nvkm_wr32(device, 0x4038, Pval);
|
||
|
|
nvkm_wr32(device, 0x4600, saved4600);
|
||
|
|
}
|
||
|
|
|
||
|
|
nvkm_wr32(device, 0xc040, savedc040);
|
||
|
|
|
||
|
|
if (mpll) {
|
||
|
|
nvkm_wr32(device, 0x4020, Pval & ~(1 << 28));
|
||
|
|
nvkm_wr32(device, 0x4038, Pval & ~(1 << 28));
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
nv04_devinit_pll_set(struct nvkm_devinit *devinit, u32 type, u32 freq)
|
||
|
|
{
|
||
|
|
struct nvkm_subdev *subdev = &devinit->subdev;
|
||
|
|
struct nvkm_bios *bios = subdev->device->bios;
|
||
|
|
struct nvkm_pll_vals pv;
|
||
|
|
struct nvbios_pll info;
|
||
|
|
int cv = bios->version.chip;
|
||
|
|
int N1, M1, N2, M2, P;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
ret = nvbios_pll_parse(bios, type > 0x405c ? type : type - 4, &info);
|
||
|
|
if (ret)
|
||
|
|
return ret;
|
||
|
|
|
||
|
|
ret = nv04_pll_calc(subdev, &info, freq, &N1, &M1, &N2, &M2, &P);
|
||
|
|
if (!ret)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
pv.refclk = info.refclk;
|
||
|
|
pv.N1 = N1;
|
||
|
|
pv.M1 = M1;
|
||
|
|
pv.N2 = N2;
|
||
|
|
pv.M2 = M2;
|
||
|
|
pv.log2P = P;
|
||
|
|
|
||
|
|
if (cv == 0x30 || cv == 0x31 || cv == 0x35 || cv == 0x36 ||
|
||
|
|
cv >= 0x40) {
|
||
|
|
if (type > 0x405c)
|
||
|
|
setPLL_double_highregs(devinit, type, &pv);
|
||
|
|
else
|
||
|
|
setPLL_double_lowregs(devinit, type, &pv);
|
||
|
|
} else
|
||
|
|
setPLL_single(devinit, type, &pv);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
nv04_devinit_post(struct nvkm_devinit *init, bool execute)
|
||
|
|
{
|
||
|
|
return nvbios_post(&init->subdev, execute);
|
||
|
|
}
|
||
|
|
|
||
|
|
void
|
||
|
|
nv04_devinit_preinit(struct nvkm_devinit *base)
|
||
|
|
{
|
||
|
|
struct nv04_devinit *init = nv04_devinit(base);
|
||
|
|
struct nvkm_subdev *subdev = &init->base.subdev;
|
||
|
|
struct nvkm_device *device = subdev->device;
|
||
|
|
|
||
|
|
/* make i2c busses accessible */
|
||
|
|
nvkm_mask(device, 0x000200, 0x00000001, 0x00000001);
|
||
|
|
|
||
|
|
/* unslave crtcs */
|
||
|
|
if (init->owner < 0)
|
||
|
|
init->owner = nvkm_rdvgaowner(device);
|
||
|
|
nvkm_wrvgaowner(device, 0);
|
||
|
|
|
||
|
|
if (!init->base.post) {
|
||
|
|
u32 htotal = nvkm_rdvgac(device, 0, 0x06);
|
||
|
|
htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x01) << 8;
|
||
|
|
htotal |= (nvkm_rdvgac(device, 0, 0x07) & 0x20) << 4;
|
||
|
|
htotal |= (nvkm_rdvgac(device, 0, 0x25) & 0x01) << 10;
|
||
|
|
htotal |= (nvkm_rdvgac(device, 0, 0x41) & 0x01) << 11;
|
||
|
|
if (!htotal) {
|
||
|
|
nvkm_debug(subdev, "adaptor not initialised\n");
|
||
|
|
init->base.post = true;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
void *
|
||
|
|
nv04_devinit_dtor(struct nvkm_devinit *base)
|
||
|
|
{
|
||
|
|
struct nv04_devinit *init = nv04_devinit(base);
|
||
|
|
/* restore vga owner saved at first init */
|
||
|
|
nvkm_wrvgaowner(init->base.subdev.device, init->owner);
|
||
|
|
return init;
|
||
|
|
}
|
||
|
|
|
||
|
|
int
|
||
|
|
nv04_devinit_new_(const struct nvkm_devinit_func *func,
|
||
|
|
struct nvkm_device *device, int index,
|
||
|
|
struct nvkm_devinit **pinit)
|
||
|
|
{
|
||
|
|
struct nv04_devinit *init;
|
||
|
|
|
||
|
|
if (!(init = kzalloc(sizeof(*init), GFP_KERNEL)))
|
||
|
|
return -ENOMEM;
|
||
|
|
*pinit = &init->base;
|
||
|
|
|
||
|
|
nvkm_devinit_ctor(func, device, index, &init->base);
|
||
|
|
init->owner = -1;
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct nvkm_devinit_func
|
||
|
|
nv04_devinit = {
|
||
|
|
.dtor = nv04_devinit_dtor,
|
||
|
|
.preinit = nv04_devinit_preinit,
|
||
|
|
.post = nv04_devinit_post,
|
||
|
|
.meminit = nv04_devinit_meminit,
|
||
|
|
.pll_set = nv04_devinit_pll_set,
|
||
|
|
};
|
||
|
|
|
||
|
|
int
|
||
|
|
nv04_devinit_new(struct nvkm_device *device, int index,
|
||
|
|
struct nvkm_devinit **pinit)
|
||
|
|
{
|
||
|
|
return nv04_devinit_new_(&nv04_devinit, device, index, pinit);
|
||
|
|
}
|