424 lines
11 KiB
C
424 lines
11 KiB
C
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#define mcp77_clk(p) container_of((p), struct mcp77_clk, base)
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#include "gt215.h"
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#include "pll.h"
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#include <subdev/bios.h>
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#include <subdev/bios/pll.h>
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#include <subdev/timer.h>
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struct mcp77_clk {
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struct nvkm_clk base;
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enum nv_clk_src csrc, ssrc, vsrc;
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u32 cctrl, sctrl;
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u32 ccoef, scoef;
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u32 cpost, spost;
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u32 vdiv;
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};
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static u32
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read_div(struct mcp77_clk *clk)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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return nvkm_rd32(device, 0x004600);
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}
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static u32
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read_pll(struct mcp77_clk *clk, u32 base)
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{
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struct nvkm_device *device = clk->base.subdev.device;
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u32 ctrl = nvkm_rd32(device, base + 0);
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u32 coef = nvkm_rd32(device, base + 4);
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u32 ref = nvkm_clk_read(&clk->base, nv_clk_src_href);
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u32 post_div = 0;
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u32 clock = 0;
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int N1, M1;
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switch (base){
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case 0x4020:
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post_div = 1 << ((nvkm_rd32(device, 0x4070) & 0x000f0000) >> 16);
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break;
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case 0x4028:
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post_div = (nvkm_rd32(device, 0x4040) & 0x000f0000) >> 16;
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break;
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default:
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break;
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}
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N1 = (coef & 0x0000ff00) >> 8;
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M1 = (coef & 0x000000ff);
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if ((ctrl & 0x80000000) && M1) {
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clock = ref * N1 / M1;
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clock = clock / post_div;
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}
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return clock;
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}
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static int
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mcp77_clk_read(struct nvkm_clk *base, enum nv_clk_src src)
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{
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struct mcp77_clk *clk = mcp77_clk(base);
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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u32 mast = nvkm_rd32(device, 0x00c054);
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u32 P = 0;
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switch (src) {
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case nv_clk_src_crystal:
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return device->crystal;
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case nv_clk_src_href:
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return 100000; /* PCIE reference clock */
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case nv_clk_src_hclkm4:
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return nvkm_clk_read(&clk->base, nv_clk_src_href) * 4;
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case nv_clk_src_hclkm2d3:
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return nvkm_clk_read(&clk->base, nv_clk_src_href) * 2 / 3;
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case nv_clk_src_host:
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switch (mast & 0x000c0000) {
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case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3);
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case 0x00040000: break;
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case 0x00080000: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4);
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case 0x000c0000: return nvkm_clk_read(&clk->base, nv_clk_src_cclk);
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}
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break;
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case nv_clk_src_core:
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P = (nvkm_rd32(device, 0x004028) & 0x00070000) >> 16;
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switch (mast & 0x00000003) {
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case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
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case 0x00000001: return 0;
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case 0x00000002: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4) >> P;
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case 0x00000003: return read_pll(clk, 0x004028) >> P;
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}
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break;
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case nv_clk_src_cclk:
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if ((mast & 0x03000000) != 0x03000000)
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return nvkm_clk_read(&clk->base, nv_clk_src_core);
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if ((mast & 0x00000200) == 0x00000000)
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return nvkm_clk_read(&clk->base, nv_clk_src_core);
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switch (mast & 0x00000c00) {
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case 0x00000000: return nvkm_clk_read(&clk->base, nv_clk_src_href);
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case 0x00000400: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm4);
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case 0x00000800: return nvkm_clk_read(&clk->base, nv_clk_src_hclkm2d3);
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default: return 0;
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}
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case nv_clk_src_shader:
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P = (nvkm_rd32(device, 0x004020) & 0x00070000) >> 16;
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switch (mast & 0x00000030) {
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case 0x00000000:
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if (mast & 0x00000040)
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return nvkm_clk_read(&clk->base, nv_clk_src_href) >> P;
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return nvkm_clk_read(&clk->base, nv_clk_src_crystal) >> P;
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case 0x00000010: break;
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case 0x00000020: return read_pll(clk, 0x004028) >> P;
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case 0x00000030: return read_pll(clk, 0x004020) >> P;
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}
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break;
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case nv_clk_src_mem:
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return 0;
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break;
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case nv_clk_src_vdec:
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P = (read_div(clk) & 0x00000700) >> 8;
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switch (mast & 0x00400000) {
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case 0x00400000:
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return nvkm_clk_read(&clk->base, nv_clk_src_core) >> P;
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break;
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default:
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return 500000 >> P;
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break;
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}
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break;
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default:
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break;
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}
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nvkm_debug(subdev, "unknown clock source %d %08x\n", src, mast);
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return 0;
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}
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static u32
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calc_pll(struct mcp77_clk *clk, u32 reg,
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u32 clock, int *N, int *M, int *P)
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{
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvbios_pll pll;
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int ret;
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ret = nvbios_pll_parse(subdev->device->bios, reg, &pll);
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if (ret)
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return 0;
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pll.vco2.max_freq = 0;
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pll.refclk = nvkm_clk_read(&clk->base, nv_clk_src_href);
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if (!pll.refclk)
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return 0;
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return nv04_pll_calc(subdev, &pll, clock, N, M, NULL, NULL, P);
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}
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static inline u32
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calc_P(u32 src, u32 target, int *div)
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{
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u32 clk0 = src, clk1 = src;
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for (*div = 0; *div <= 7; (*div)++) {
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if (clk0 <= target) {
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clk1 = clk0 << (*div ? 1 : 0);
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break;
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}
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clk0 >>= 1;
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}
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if (target - clk0 <= clk1 - target)
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return clk0;
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(*div)--;
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return clk1;
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}
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static int
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mcp77_clk_calc(struct nvkm_clk *base, struct nvkm_cstate *cstate)
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{
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struct mcp77_clk *clk = mcp77_clk(base);
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const int shader = cstate->domain[nv_clk_src_shader];
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const int core = cstate->domain[nv_clk_src_core];
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const int vdec = cstate->domain[nv_clk_src_vdec];
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struct nvkm_subdev *subdev = &clk->base.subdev;
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u32 out = 0, clock = 0;
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int N, M, P1, P2 = 0;
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int divs = 0;
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/* cclk: find suitable source, disable PLL if we can */
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if (core < nvkm_clk_read(&clk->base, nv_clk_src_hclkm4))
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out = calc_P(nvkm_clk_read(&clk->base, nv_clk_src_hclkm4), core, &divs);
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/* Calculate clock * 2, so shader clock can use it too */
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clock = calc_pll(clk, 0x4028, (core << 1), &N, &M, &P1);
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if (abs(core - out) <= abs(core - (clock >> 1))) {
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clk->csrc = nv_clk_src_hclkm4;
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clk->cctrl = divs << 16;
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} else {
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/* NVCTRL is actually used _after_ NVPOST, and after what we
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* call NVPLL. To make matters worse, NVPOST is an integer
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* divider instead of a right-shift number. */
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if(P1 > 2) {
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P2 = P1 - 2;
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P1 = 2;
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}
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clk->csrc = nv_clk_src_core;
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clk->ccoef = (N << 8) | M;
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clk->cctrl = (P2 + 1) << 16;
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clk->cpost = (1 << P1) << 16;
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}
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/* sclk: nvpll + divisor, href or spll */
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out = 0;
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if (shader == nvkm_clk_read(&clk->base, nv_clk_src_href)) {
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clk->ssrc = nv_clk_src_href;
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} else {
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clock = calc_pll(clk, 0x4020, shader, &N, &M, &P1);
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if (clk->csrc == nv_clk_src_core)
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out = calc_P((core << 1), shader, &divs);
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if (abs(shader - out) <=
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abs(shader - clock) &&
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(divs + P2) <= 7) {
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clk->ssrc = nv_clk_src_core;
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clk->sctrl = (divs + P2) << 16;
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} else {
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clk->ssrc = nv_clk_src_shader;
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clk->scoef = (N << 8) | M;
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clk->sctrl = P1 << 16;
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}
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}
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/* vclk */
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out = calc_P(core, vdec, &divs);
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clock = calc_P(500000, vdec, &P1);
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if(abs(vdec - out) <= abs(vdec - clock)) {
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clk->vsrc = nv_clk_src_cclk;
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clk->vdiv = divs << 16;
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} else {
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clk->vsrc = nv_clk_src_vdec;
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clk->vdiv = P1 << 16;
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}
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/* Print strategy! */
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nvkm_debug(subdev, "nvpll: %08x %08x %08x\n",
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clk->ccoef, clk->cpost, clk->cctrl);
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nvkm_debug(subdev, " spll: %08x %08x %08x\n",
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clk->scoef, clk->spost, clk->sctrl);
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nvkm_debug(subdev, " vdiv: %08x\n", clk->vdiv);
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if (clk->csrc == nv_clk_src_hclkm4)
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nvkm_debug(subdev, "core: hrefm4\n");
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else
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nvkm_debug(subdev, "core: nvpll\n");
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if (clk->ssrc == nv_clk_src_hclkm4)
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nvkm_debug(subdev, "shader: hrefm4\n");
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else if (clk->ssrc == nv_clk_src_core)
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nvkm_debug(subdev, "shader: nvpll\n");
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else
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nvkm_debug(subdev, "shader: spll\n");
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if (clk->vsrc == nv_clk_src_hclkm4)
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nvkm_debug(subdev, "vdec: 500MHz\n");
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else
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nvkm_debug(subdev, "vdec: core\n");
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return 0;
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}
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static int
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mcp77_clk_prog(struct nvkm_clk *base)
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{
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struct mcp77_clk *clk = mcp77_clk(base);
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struct nvkm_subdev *subdev = &clk->base.subdev;
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struct nvkm_device *device = subdev->device;
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u32 pllmask = 0, mast;
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unsigned long flags;
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unsigned long *f = &flags;
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int ret = 0;
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ret = gt215_clk_pre(&clk->base, f);
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if (ret)
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goto out;
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/* First switch to safe clocks: href */
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mast = nvkm_mask(device, 0xc054, 0x03400e70, 0x03400640);
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mast &= ~0x00400e73;
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mast |= 0x03000000;
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switch (clk->csrc) {
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case nv_clk_src_hclkm4:
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nvkm_mask(device, 0x4028, 0x00070000, clk->cctrl);
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mast |= 0x00000002;
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break;
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case nv_clk_src_core:
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nvkm_wr32(device, 0x402c, clk->ccoef);
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nvkm_wr32(device, 0x4028, 0x80000000 | clk->cctrl);
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nvkm_wr32(device, 0x4040, clk->cpost);
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pllmask |= (0x3 << 8);
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mast |= 0x00000003;
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break;
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default:
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nvkm_warn(subdev, "Reclocking failed: unknown core clock\n");
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goto resume;
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}
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switch (clk->ssrc) {
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case nv_clk_src_href:
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nvkm_mask(device, 0x4020, 0x00070000, 0x00000000);
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/* mast |= 0x00000000; */
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break;
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case nv_clk_src_core:
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nvkm_mask(device, 0x4020, 0x00070000, clk->sctrl);
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mast |= 0x00000020;
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break;
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case nv_clk_src_shader:
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nvkm_wr32(device, 0x4024, clk->scoef);
|
||
|
|
nvkm_wr32(device, 0x4020, 0x80000000 | clk->sctrl);
|
||
|
|
nvkm_wr32(device, 0x4070, clk->spost);
|
||
|
|
pllmask |= (0x3 << 12);
|
||
|
|
mast |= 0x00000030;
|
||
|
|
break;
|
||
|
|
default:
|
||
|
|
nvkm_warn(subdev, "Reclocking failed: unknown sclk clock\n");
|
||
|
|
goto resume;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (nvkm_msec(device, 2000,
|
||
|
|
u32 tmp = nvkm_rd32(device, 0x004080) & pllmask;
|
||
|
|
if (tmp == pllmask)
|
||
|
|
break;
|
||
|
|
) < 0)
|
||
|
|
goto resume;
|
||
|
|
|
||
|
|
switch (clk->vsrc) {
|
||
|
|
case nv_clk_src_cclk:
|
||
|
|
mast |= 0x00400000;
|
||
|
|
default:
|
||
|
|
nvkm_wr32(device, 0x4600, clk->vdiv);
|
||
|
|
}
|
||
|
|
|
||
|
|
nvkm_wr32(device, 0xc054, mast);
|
||
|
|
|
||
|
|
resume:
|
||
|
|
/* Disable some PLLs and dividers when unused */
|
||
|
|
if (clk->csrc != nv_clk_src_core) {
|
||
|
|
nvkm_wr32(device, 0x4040, 0x00000000);
|
||
|
|
nvkm_mask(device, 0x4028, 0x80000000, 0x00000000);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (clk->ssrc != nv_clk_src_shader) {
|
||
|
|
nvkm_wr32(device, 0x4070, 0x00000000);
|
||
|
|
nvkm_mask(device, 0x4020, 0x80000000, 0x00000000);
|
||
|
|
}
|
||
|
|
|
||
|
|
out:
|
||
|
|
if (ret == -EBUSY)
|
||
|
|
f = NULL;
|
||
|
|
|
||
|
|
gt215_clk_post(&clk->base, f);
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
static void
|
||
|
|
mcp77_clk_tidy(struct nvkm_clk *base)
|
||
|
|
{
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct nvkm_clk_func
|
||
|
|
mcp77_clk = {
|
||
|
|
.read = mcp77_clk_read,
|
||
|
|
.calc = mcp77_clk_calc,
|
||
|
|
.prog = mcp77_clk_prog,
|
||
|
|
.tidy = mcp77_clk_tidy,
|
||
|
|
.domains = {
|
||
|
|
{ nv_clk_src_crystal, 0xff },
|
||
|
|
{ nv_clk_src_href , 0xff },
|
||
|
|
{ nv_clk_src_core , 0xff, 0, "core", 1000 },
|
||
|
|
{ nv_clk_src_shader , 0xff, 0, "shader", 1000 },
|
||
|
|
{ nv_clk_src_vdec , 0xff, 0, "vdec", 1000 },
|
||
|
|
{ nv_clk_src_max }
|
||
|
|
}
|
||
|
|
};
|
||
|
|
|
||
|
|
int
|
||
|
|
mcp77_clk_new(struct nvkm_device *device, int index, struct nvkm_clk **pclk)
|
||
|
|
{
|
||
|
|
struct mcp77_clk *clk;
|
||
|
|
|
||
|
|
if (!(clk = kzalloc(sizeof(*clk), GFP_KERNEL)))
|
||
|
|
return -ENOMEM;
|
||
|
|
*pclk = &clk->base;
|
||
|
|
|
||
|
|
return nvkm_clk_ctor(&mcp77_clk, device, index, true, &clk->base);
|
||
|
|
}
|