216 lines
5.9 KiB
C
216 lines
5.9 KiB
C
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/*
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* Copyright 2012 Nouveau Community
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Martin Peres
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*/
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#include <subdev/bios.h>
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#include <subdev/bios/bit.h>
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#include <subdev/bios/perf.h>
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#include <subdev/pci.h>
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u32
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nvbios_perf_table(struct nvkm_bios *bios, u8 *ver, u8 *hdr,
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u8 *cnt, u8 *len, u8 *snr, u8 *ssz)
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{
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struct bit_entry bit_P;
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u32 perf = 0;
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if (!bit_entry(bios, 'P', &bit_P)) {
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if (bit_P.version <= 2) {
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perf = nvbios_rd32(bios, bit_P.offset + 0);
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if (perf) {
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*ver = nvbios_rd08(bios, perf + 0);
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*hdr = nvbios_rd08(bios, perf + 1);
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if (*ver >= 0x40 && *ver < 0x41) {
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*cnt = nvbios_rd08(bios, perf + 5);
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*len = nvbios_rd08(bios, perf + 2);
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*snr = nvbios_rd08(bios, perf + 4);
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*ssz = nvbios_rd08(bios, perf + 3);
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return perf;
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} else
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if (*ver >= 0x20 && *ver < 0x40) {
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*cnt = nvbios_rd08(bios, perf + 2);
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*len = nvbios_rd08(bios, perf + 3);
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*snr = nvbios_rd08(bios, perf + 4);
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*ssz = nvbios_rd08(bios, perf + 5);
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return perf;
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}
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}
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}
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}
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if (bios->bmp_offset) {
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if (nvbios_rd08(bios, bios->bmp_offset + 6) >= 0x25) {
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perf = nvbios_rd16(bios, bios->bmp_offset + 0x94);
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if (perf) {
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*hdr = nvbios_rd08(bios, perf + 0);
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*ver = nvbios_rd08(bios, perf + 1);
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*cnt = nvbios_rd08(bios, perf + 2);
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*len = nvbios_rd08(bios, perf + 3);
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*snr = 0;
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*ssz = 0;
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return perf;
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}
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}
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}
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return 0;
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}
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u32
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nvbios_perf_entry(struct nvkm_bios *bios, int idx,
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u8 *ver, u8 *hdr, u8 *cnt, u8 *len)
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{
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u8 snr, ssz;
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u32 perf = nvbios_perf_table(bios, ver, hdr, cnt, len, &snr, &ssz);
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if (perf && idx < *cnt) {
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perf = perf + *hdr + (idx * (*len + (snr * ssz)));
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*hdr = *len;
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*cnt = snr;
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*len = ssz;
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return perf;
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}
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return 0;
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}
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u32
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nvbios_perfEp(struct nvkm_bios *bios, int idx,
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u8 *ver, u8 *hdr, u8 *cnt, u8 *len, struct nvbios_perfE *info)
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{
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u32 perf = nvbios_perf_entry(bios, idx, ver, hdr, cnt, len);
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memset(info, 0x00, sizeof(*info));
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info->pstate = nvbios_rd08(bios, perf + 0x00);
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switch (!!perf * *ver) {
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case 0x12:
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case 0x13:
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case 0x14:
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info->core = nvbios_rd32(bios, perf + 0x01) * 10;
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info->memory = nvbios_rd32(bios, perf + 0x05) * 20;
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info->fanspeed = nvbios_rd08(bios, perf + 0x37);
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if (*hdr > 0x38)
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info->voltage = nvbios_rd08(bios, perf + 0x38);
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break;
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case 0x21:
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case 0x23:
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case 0x24:
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info->fanspeed = nvbios_rd08(bios, perf + 0x04);
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info->voltage = nvbios_rd08(bios, perf + 0x05);
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info->shader = nvbios_rd16(bios, perf + 0x06) * 1000;
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info->core = info->shader + (signed char)
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nvbios_rd08(bios, perf + 0x08) * 1000;
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switch (bios->subdev.device->chipset) {
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case 0x49:
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case 0x4b:
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info->memory = nvbios_rd16(bios, perf + 0x0b) * 1000;
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break;
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default:
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info->memory = nvbios_rd16(bios, perf + 0x0b) * 2000;
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break;
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}
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break;
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case 0x25:
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info->fanspeed = nvbios_rd08(bios, perf + 0x04);
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info->voltage = nvbios_rd08(bios, perf + 0x05);
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info->core = nvbios_rd16(bios, perf + 0x06) * 1000;
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info->shader = nvbios_rd16(bios, perf + 0x0a) * 1000;
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info->memory = nvbios_rd16(bios, perf + 0x0c) * 1000;
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break;
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case 0x30:
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info->script = nvbios_rd16(bios, perf + 0x02);
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case 0x35:
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info->fanspeed = nvbios_rd08(bios, perf + 0x06);
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info->voltage = nvbios_rd08(bios, perf + 0x07);
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info->core = nvbios_rd16(bios, perf + 0x08) * 1000;
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info->shader = nvbios_rd16(bios, perf + 0x0a) * 1000;
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info->memory = nvbios_rd16(bios, perf + 0x0c) * 1000;
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info->vdec = nvbios_rd16(bios, perf + 0x10) * 1000;
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info->disp = nvbios_rd16(bios, perf + 0x14) * 1000;
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break;
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case 0x40:
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info->voltage = nvbios_rd08(bios, perf + 0x02);
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switch (nvbios_rd08(bios, perf + 0xb) & 0x3) {
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case 0:
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info->pcie_speed = NVKM_PCIE_SPEED_5_0;
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break;
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case 3:
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case 1:
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info->pcie_speed = NVKM_PCIE_SPEED_2_5;
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break;
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case 2:
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info->pcie_speed = NVKM_PCIE_SPEED_8_0;
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break;
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default:
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break;
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}
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info->pcie_width = 0xff;
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break;
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default:
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return 0;
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}
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return perf;
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}
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u32
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nvbios_perfSe(struct nvkm_bios *bios, u32 perfE, int idx,
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u8 *ver, u8 *hdr, u8 cnt, u8 len)
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{
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u32 data = 0x00000000;
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if (idx < cnt) {
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data = perfE + *hdr + (idx * len);
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*hdr = len;
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}
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return data;
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}
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u32
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nvbios_perfSp(struct nvkm_bios *bios, u32 perfE, int idx,
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u8 *ver, u8 *hdr, u8 cnt, u8 len,
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struct nvbios_perfS *info)
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{
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u32 data = nvbios_perfSe(bios, perfE, idx, ver, hdr, cnt, len);
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memset(info, 0x00, sizeof(*info));
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switch (!!data * *ver) {
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case 0x40:
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info->v40.freq = (nvbios_rd16(bios, data + 0x00) & 0x3fff) * 1000;
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break;
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default:
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break;
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}
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return data;
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}
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int
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nvbios_perf_fan_parse(struct nvkm_bios *bios,
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struct nvbios_perf_fan *fan)
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{
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u8 ver, hdr, cnt, len, snr, ssz;
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u32 perf = nvbios_perf_table(bios, &ver, &hdr, &cnt, &len, &snr, &ssz);
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if (!perf)
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return -ENODEV;
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if (ver >= 0x20 && ver < 0x40 && hdr > 6)
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fan->pwm_divisor = nvbios_rd16(bios, perf + 6);
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else
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fan->pwm_divisor = 0;
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return 0;
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}
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