387 lines
11 KiB
C
387 lines
11 KiB
C
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/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "changk104.h"
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#include <core/client.h>
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#include <core/gpuobj.h>
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#include <subdev/fb.h>
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#include <subdev/mmu.h>
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#include <subdev/timer.h>
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#include <nvif/class.h>
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#include <nvif/cla06f.h>
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#include <nvif/unpack.h>
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static int
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gk104_fifo_gpfifo_kick(struct gk104_fifo_chan *chan)
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{
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struct gk104_fifo *fifo = chan->fifo;
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_client *client = chan->base.object.client;
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int ret = 0;
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mutex_lock(&subdev->mutex);
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nvkm_wr32(device, 0x002634, chan->base.chid);
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if (nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x002634) & 0x00100000))
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break;
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) < 0) {
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nvkm_error(subdev, "channel %d [%s] kick timeout\n",
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chan->base.chid, client->name);
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nvkm_fifo_recover_chan(&fifo->base, chan->base.chid);
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ret = -ETIMEDOUT;
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}
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mutex_unlock(&subdev->mutex);
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return ret;
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}
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static u32
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gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
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{
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switch (engine->subdev.index) {
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case NVKM_ENGINE_SW :
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case NVKM_ENGINE_CE0 :
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case NVKM_ENGINE_CE1 :
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case NVKM_ENGINE_CE2 : return 0x0000;
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case NVKM_ENGINE_GR : return 0x0210;
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case NVKM_ENGINE_SEC : return 0x0220;
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case NVKM_ENGINE_MSPDEC: return 0x0250;
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case NVKM_ENGINE_MSPPP : return 0x0260;
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case NVKM_ENGINE_MSVLD : return 0x0270;
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case NVKM_ENGINE_VIC : return 0x0280;
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case NVKM_ENGINE_MSENC : return 0x0290;
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case NVKM_ENGINE_NVDEC : return 0x02100270;
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case NVKM_ENGINE_NVENC0: return 0x02100290;
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case NVKM_ENGINE_NVENC1: return 0x0210;
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default:
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WARN_ON(1);
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return 0;
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}
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}
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static int
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gk104_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine, bool suspend)
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{
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struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
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struct nvkm_gpuobj *inst = chan->base.inst;
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u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
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int ret;
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ret = gk104_fifo_gpfifo_kick(chan);
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if (ret && suspend)
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return ret;
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if (offset) {
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nvkm_kmap(inst);
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nvkm_wo32(inst, (offset & 0xffff) + 0x00, 0x00000000);
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nvkm_wo32(inst, (offset & 0xffff) + 0x04, 0x00000000);
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if ((offset >>= 16)) {
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nvkm_wo32(inst, offset + 0x00, 0x00000000);
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nvkm_wo32(inst, offset + 0x04, 0x00000000);
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}
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nvkm_done(inst);
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}
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return ret;
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}
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static int
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gk104_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine)
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{
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struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
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struct nvkm_gpuobj *inst = chan->base.inst;
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u32 offset = gk104_fifo_gpfifo_engine_addr(engine);
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if (offset) {
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u64 addr = chan->engn[engine->subdev.index].vma->addr;
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u32 datalo = lower_32_bits(addr) | 0x00000004;
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u32 datahi = upper_32_bits(addr);
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nvkm_kmap(inst);
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nvkm_wo32(inst, (offset & 0xffff) + 0x00, datalo);
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nvkm_wo32(inst, (offset & 0xffff) + 0x04, datahi);
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if ((offset >>= 16)) {
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nvkm_wo32(inst, offset + 0x00, datalo);
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nvkm_wo32(inst, offset + 0x04, datahi);
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}
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nvkm_done(inst);
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}
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return 0;
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}
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static void
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gk104_fifo_gpfifo_engine_dtor(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine)
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{
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struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
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nvkm_vmm_put(chan->base.vmm, &chan->engn[engine->subdev.index].vma);
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nvkm_gpuobj_del(&chan->engn[engine->subdev.index].inst);
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}
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static int
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gk104_fifo_gpfifo_engine_ctor(struct nvkm_fifo_chan *base,
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struct nvkm_engine *engine,
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struct nvkm_object *object)
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{
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struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
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int engn = engine->subdev.index;
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int ret;
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if (!gk104_fifo_gpfifo_engine_addr(engine))
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return 0;
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ret = nvkm_object_bind(object, NULL, 0, &chan->engn[engn].inst);
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if (ret)
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return ret;
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ret = nvkm_vmm_get(chan->base.vmm, 12, chan->engn[engn].inst->size,
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&chan->engn[engn].vma);
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if (ret)
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return ret;
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return nvkm_memory_map(chan->engn[engn].inst, 0, chan->base.vmm,
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chan->engn[engn].vma, NULL, 0);
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}
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static void
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gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base)
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{
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struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
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struct gk104_fifo *fifo = chan->fifo;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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u32 coff = chan->base.chid * 8;
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if (!list_empty(&chan->head)) {
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gk104_fifo_runlist_remove(fifo, chan);
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nvkm_mask(device, 0x800004 + coff, 0x00000800, 0x00000800);
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gk104_fifo_gpfifo_kick(chan);
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gk104_fifo_runlist_commit(fifo, chan->runl);
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}
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nvkm_wr32(device, 0x800000 + coff, 0x00000000);
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}
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static void
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gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
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{
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struct gk104_fifo_chan *chan = gk104_fifo_chan(base);
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struct gk104_fifo *fifo = chan->fifo;
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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u32 addr = chan->base.inst->addr >> 12;
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u32 coff = chan->base.chid * 8;
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nvkm_mask(device, 0x800004 + coff, 0x000f0000, chan->runl << 16);
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nvkm_wr32(device, 0x800000 + coff, 0x80000000 | addr);
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if (list_empty(&chan->head) && !chan->killed) {
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gk104_fifo_runlist_insert(fifo, chan);
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nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
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gk104_fifo_runlist_commit(fifo, chan->runl);
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nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
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}
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}
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static void *
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gk104_fifo_gpfifo_dtor(struct nvkm_fifo_chan *base)
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{
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return gk104_fifo_chan(base);
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}
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static const struct nvkm_fifo_chan_func
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gk104_fifo_gpfifo_func = {
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.dtor = gk104_fifo_gpfifo_dtor,
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.init = gk104_fifo_gpfifo_init,
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.fini = gk104_fifo_gpfifo_fini,
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.ntfy = gf100_fifo_chan_ntfy,
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.engine_ctor = gk104_fifo_gpfifo_engine_ctor,
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.engine_dtor = gk104_fifo_gpfifo_engine_dtor,
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.engine_init = gk104_fifo_gpfifo_engine_init,
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.engine_fini = gk104_fifo_gpfifo_engine_fini,
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};
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struct gk104_fifo_chan_func {
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u32 engine;
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u64 subdev;
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};
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static int
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gk104_fifo_gpfifo_new_(const struct gk104_fifo_chan_func *func,
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struct gk104_fifo *fifo, u32 *engmask, u16 *chid,
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u64 vmm, u64 ioffset, u64 ilength,
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const struct nvkm_oclass *oclass,
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struct nvkm_object **pobject)
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{
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struct gk104_fifo_chan *chan;
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int runlist = -1, ret = -ENOSYS, i, j;
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u32 engines = 0, present = 0;
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u64 subdevs = 0;
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u64 usermem;
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if (!vmm)
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return -EINVAL;
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/* Determine which downstream engines are present */
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for (i = 0; i < fifo->engine_nr; i++) {
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struct nvkm_engine *engine = fifo->engine[i].engine;
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if (engine) {
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u64 submask = BIT_ULL(engine->subdev.index);
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for (j = 0; func[j].subdev; j++) {
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if (func[j].subdev & submask) {
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present |= func[j].engine;
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break;
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}
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}
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if (!func[j].subdev)
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continue;
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if (runlist < 0 && (*engmask & present))
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runlist = fifo->engine[i].runl;
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if (runlist == fifo->engine[i].runl) {
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engines |= func[j].engine;
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subdevs |= func[j].subdev;
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}
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}
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}
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/* Just an engine mask query? All done here! */
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if (!*engmask) {
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*engmask = present;
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return nvkm_object_new(oclass, NULL, 0, pobject);
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}
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/* No runlist? No supported engines. */
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*engmask = present;
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if (runlist < 0)
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return -ENODEV;
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*engmask = engines;
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/* Allocate the channel. */
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if (!(chan = kzalloc(sizeof(*chan), GFP_KERNEL)))
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return -ENOMEM;
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*pobject = &chan->base.object;
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chan->fifo = fifo;
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chan->runl = runlist;
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INIT_LIST_HEAD(&chan->head);
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ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base,
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0x1000, 0x1000, true, vmm, 0, subdevs,
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1, fifo->user.bar->addr, 0x200,
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oclass, &chan->base);
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if (ret)
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return ret;
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*chid = chan->base.chid;
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/* Clear channel control registers. */
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usermem = chan->base.chid * 0x200;
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ilength = order_base_2(ilength / 8);
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nvkm_kmap(fifo->user.mem);
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for (i = 0; i < 0x200; i += 4)
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nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000);
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nvkm_done(fifo->user.mem);
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usermem = nvkm_memory_addr(fifo->user.mem) + usermem;
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/* RAMFC */
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nvkm_kmap(chan->base.inst);
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nvkm_wo32(chan->base.inst, 0x08, lower_32_bits(usermem));
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nvkm_wo32(chan->base.inst, 0x0c, upper_32_bits(usermem));
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nvkm_wo32(chan->base.inst, 0x10, 0x0000face);
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nvkm_wo32(chan->base.inst, 0x30, 0xfffff902);
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nvkm_wo32(chan->base.inst, 0x48, lower_32_bits(ioffset));
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nvkm_wo32(chan->base.inst, 0x4c, upper_32_bits(ioffset) |
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(ilength << 16));
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nvkm_wo32(chan->base.inst, 0x84, 0x20400000);
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nvkm_wo32(chan->base.inst, 0x94, 0x30000001);
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nvkm_wo32(chan->base.inst, 0x9c, 0x00000100);
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nvkm_wo32(chan->base.inst, 0xac, 0x0000001f);
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nvkm_wo32(chan->base.inst, 0xe8, chan->base.chid);
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nvkm_wo32(chan->base.inst, 0xb8, 0xf8000000);
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nvkm_wo32(chan->base.inst, 0xf8, 0x10003080); /* 0x002310 */
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nvkm_wo32(chan->base.inst, 0xfc, 0x10000010); /* 0x002350 */
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nvkm_done(chan->base.inst);
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return 0;
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}
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static const struct gk104_fifo_chan_func
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gk104_fifo_gpfifo[] = {
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{ NVA06F_V0_ENGINE_SW | NVA06F_V0_ENGINE_GR,
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BIT_ULL(NVKM_ENGINE_SW) | BIT_ULL(NVKM_ENGINE_GR)
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},
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{ NVA06F_V0_ENGINE_SEC , BIT_ULL(NVKM_ENGINE_SEC ) },
|
||
|
|
{ NVA06F_V0_ENGINE_MSVLD , BIT_ULL(NVKM_ENGINE_MSVLD ) },
|
||
|
|
{ NVA06F_V0_ENGINE_MSPDEC, BIT_ULL(NVKM_ENGINE_MSPDEC) },
|
||
|
|
{ NVA06F_V0_ENGINE_MSPPP , BIT_ULL(NVKM_ENGINE_MSPPP ) },
|
||
|
|
{ NVA06F_V0_ENGINE_MSENC , BIT_ULL(NVKM_ENGINE_MSENC ) },
|
||
|
|
{ NVA06F_V0_ENGINE_VIC , BIT_ULL(NVKM_ENGINE_VIC ) },
|
||
|
|
{ NVA06F_V0_ENGINE_NVDEC , BIT_ULL(NVKM_ENGINE_NVDEC ) },
|
||
|
|
{ NVA06F_V0_ENGINE_NVENC0, BIT_ULL(NVKM_ENGINE_NVENC0) },
|
||
|
|
{ NVA06F_V0_ENGINE_NVENC1, BIT_ULL(NVKM_ENGINE_NVENC1) },
|
||
|
|
{ NVA06F_V0_ENGINE_CE0 , BIT_ULL(NVKM_ENGINE_CE0 ) },
|
||
|
|
{ NVA06F_V0_ENGINE_CE1 , BIT_ULL(NVKM_ENGINE_CE1 ) },
|
||
|
|
{ NVA06F_V0_ENGINE_CE2 , BIT_ULL(NVKM_ENGINE_CE2 ) },
|
||
|
|
{}
|
||
|
|
};
|
||
|
|
|
||
|
|
int
|
||
|
|
gk104_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
|
||
|
|
void *data, u32 size, struct nvkm_object **pobject)
|
||
|
|
{
|
||
|
|
struct nvkm_object *parent = oclass->parent;
|
||
|
|
union {
|
||
|
|
struct kepler_channel_gpfifo_a_v0 v0;
|
||
|
|
} *args = data;
|
||
|
|
struct gk104_fifo *fifo = gk104_fifo(base);
|
||
|
|
int ret = -ENOSYS;
|
||
|
|
|
||
|
|
nvif_ioctl(parent, "create channel gpfifo size %d\n", size);
|
||
|
|
if (!(ret = nvif_unpack(ret, &data, &size, args->v0, 0, 0, false))) {
|
||
|
|
nvif_ioctl(parent, "create channel gpfifo vers %d vmm %llx "
|
||
|
|
"ioffset %016llx ilength %08x engine %08x\n",
|
||
|
|
args->v0.version, args->v0.vmm, args->v0.ioffset,
|
||
|
|
args->v0.ilength, args->v0.engines);
|
||
|
|
return gk104_fifo_gpfifo_new_(gk104_fifo_gpfifo, fifo,
|
||
|
|
&args->v0.engines,
|
||
|
|
&args->v0.chid,
|
||
|
|
args->v0.vmm,
|
||
|
|
args->v0.ioffset,
|
||
|
|
args->v0.ilength,
|
||
|
|
oclass, pobject);
|
||
|
|
}
|
||
|
|
|
||
|
|
return ret;
|
||
|
|
}
|
||
|
|
|
||
|
|
const struct nvkm_fifo_chan_oclass
|
||
|
|
gk104_fifo_gpfifo_oclass = {
|
||
|
|
.base.oclass = KEPLER_CHANNEL_GPFIFO_A,
|
||
|
|
.base.minver = 0,
|
||
|
|
.base.maxver = 0,
|
||
|
|
.ctor = gk104_fifo_gpfifo_new,
|
||
|
|
};
|