446 lines
13 KiB
C
446 lines
13 KiB
C
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/*
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* Copyright (c) 2014, The Linux Foundation. All rights reserved.
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include "mdp5_kms.h"
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static struct mdp5_kms *get_kms(struct drm_encoder *encoder)
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{
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struct msm_drm_private *priv = encoder->dev->dev_private;
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return to_mdp5_kms(to_mdp_kms(priv->kms));
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}
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#ifdef DOWNSTREAM_CONFIG_MSM_BUS_SCALING
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#include <mach/board.h>
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#include <mach/msm_bus.h>
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#include <mach/msm_bus_board.h>
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#define MDP_BUS_VECTOR_ENTRY(ab_val, ib_val) \
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{ \
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.src = MSM_BUS_MASTER_MDP_PORT0, \
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.dst = MSM_BUS_SLAVE_EBI_CH0, \
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.ab = (ab_val), \
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.ib = (ib_val), \
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}
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static struct msm_bus_vectors mdp_bus_vectors[] = {
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MDP_BUS_VECTOR_ENTRY(0, 0),
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MDP_BUS_VECTOR_ENTRY(2000000000, 2000000000),
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};
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static struct msm_bus_paths mdp_bus_usecases[] = { {
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.num_paths = 1,
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.vectors = &mdp_bus_vectors[0],
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}, {
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.num_paths = 1,
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.vectors = &mdp_bus_vectors[1],
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} };
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static struct msm_bus_scale_pdata mdp_bus_scale_table = {
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.usecase = mdp_bus_usecases,
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.num_usecases = ARRAY_SIZE(mdp_bus_usecases),
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.name = "mdss_mdp",
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};
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static void bs_init(struct mdp5_encoder *mdp5_encoder)
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{
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mdp5_encoder->bsc = msm_bus_scale_register_client(
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&mdp_bus_scale_table);
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DBG("bus scale client: %08x", mdp5_encoder->bsc);
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}
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static void bs_fini(struct mdp5_encoder *mdp5_encoder)
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{
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if (mdp5_encoder->bsc) {
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msm_bus_scale_unregister_client(mdp5_encoder->bsc);
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mdp5_encoder->bsc = 0;
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}
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}
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static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx)
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{
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if (mdp5_encoder->bsc) {
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DBG("set bus scaling: %d", idx);
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/* HACK: scaling down, and then immediately back up
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* seems to leave things broken (underflow).. so
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* never disable:
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*/
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idx = 1;
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msm_bus_scale_client_update_request(mdp5_encoder->bsc, idx);
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}
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}
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#else
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static void bs_init(struct mdp5_encoder *mdp5_encoder) {}
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static void bs_fini(struct mdp5_encoder *mdp5_encoder) {}
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static void bs_set(struct mdp5_encoder *mdp5_encoder, int idx) {}
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#endif
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static void mdp5_encoder_destroy(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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bs_fini(mdp5_encoder);
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drm_encoder_cleanup(encoder);
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kfree(mdp5_encoder);
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}
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static const struct drm_encoder_funcs mdp5_encoder_funcs = {
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.destroy = mdp5_encoder_destroy,
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};
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static void mdp5_vid_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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struct drm_device *dev = encoder->dev;
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struct drm_connector *connector;
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int intf = mdp5_encoder->intf->num;
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uint32_t dtv_hsync_skew, vsync_period, vsync_len, ctrl_pol;
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uint32_t display_v_start, display_v_end;
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uint32_t hsync_start_x, hsync_end_x;
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uint32_t format = 0x2100;
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unsigned long flags;
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mode = adjusted_mode;
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DBG("set mode: %d:\"%s\" %d %d %d %d %d %d %d %d %d %d 0x%x 0x%x",
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mode->base.id, mode->name,
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mode->vrefresh, mode->clock,
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mode->hdisplay, mode->hsync_start,
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mode->hsync_end, mode->htotal,
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mode->vdisplay, mode->vsync_start,
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mode->vsync_end, mode->vtotal,
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mode->type, mode->flags);
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ctrl_pol = 0;
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/* DSI controller cannot handle active-low sync signals. */
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if (mdp5_encoder->intf->type != INTF_DSI) {
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if (mode->flags & DRM_MODE_FLAG_NHSYNC)
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ctrl_pol |= MDP5_INTF_POLARITY_CTL_HSYNC_LOW;
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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ctrl_pol |= MDP5_INTF_POLARITY_CTL_VSYNC_LOW;
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}
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/* probably need to get DATA_EN polarity from panel.. */
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dtv_hsync_skew = 0; /* get this from panel? */
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/* Get color format from panel, default is 8bpc */
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list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder) {
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switch (connector->display_info.bpc) {
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case 4:
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format |= 0;
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break;
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case 5:
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format |= 0x15;
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break;
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case 6:
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format |= 0x2A;
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break;
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case 8:
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default:
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format |= 0x3F;
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break;
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}
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break;
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}
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}
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hsync_start_x = (mode->htotal - mode->hsync_start);
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hsync_end_x = mode->htotal - (mode->hsync_start - mode->hdisplay) - 1;
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vsync_period = mode->vtotal * mode->htotal;
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vsync_len = (mode->vsync_end - mode->vsync_start) * mode->htotal;
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display_v_start = (mode->vtotal - mode->vsync_start) * mode->htotal + dtv_hsync_skew;
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display_v_end = vsync_period - ((mode->vsync_start - mode->vdisplay) * mode->htotal) + dtv_hsync_skew - 1;
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/*
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* For edp only:
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* DISPLAY_V_START = (VBP * HCYCLE) + HBP
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* DISPLAY_V_END = (VBP + VACTIVE) * HCYCLE - 1 - HFP
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*/
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if (mdp5_encoder->intf->type == INTF_eDP) {
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display_v_start += mode->htotal - mode->hsync_start;
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display_v_end -= mode->hsync_start - mode->hdisplay;
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}
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spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_CTL(intf),
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MDP5_INTF_HSYNC_CTL_PULSEW(mode->hsync_end - mode->hsync_start) |
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MDP5_INTF_HSYNC_CTL_PERIOD(mode->htotal));
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mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_PERIOD_F0(intf), vsync_period);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_VSYNC_LEN_F0(intf), vsync_len);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_HCTL(intf),
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MDP5_INTF_DISPLAY_HCTL_START(hsync_start_x) |
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MDP5_INTF_DISPLAY_HCTL_END(hsync_end_x));
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mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VSTART_F0(intf), display_v_start);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_DISPLAY_VEND_F0(intf), display_v_end);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_BORDER_COLOR(intf), 0);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_UNDERFLOW_COLOR(intf), 0xff);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_HSYNC_SKEW(intf), dtv_hsync_skew);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_POLARITY_CTL(intf), ctrl_pol);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_HCTL(intf),
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MDP5_INTF_ACTIVE_HCTL_START(0) |
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MDP5_INTF_ACTIVE_HCTL_END(0));
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mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VSTART_F0(intf), 0);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_ACTIVE_VEND_F0(intf), 0);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_PANEL_FORMAT(intf), format);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_FRAME_LINE_COUNT_EN(intf), 0x3); /* frame+line? */
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spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
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mdp5_crtc_set_pipeline(encoder->crtc);
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}
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static void mdp5_vid_encoder_disable(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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struct mdp5_ctl *ctl = mdp5_encoder->ctl;
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struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
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struct mdp5_hw_mixer *mixer = mdp5_crtc_get_mixer(encoder->crtc);
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struct mdp5_interface *intf = mdp5_encoder->intf;
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int intfn = mdp5_encoder->intf->num;
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unsigned long flags;
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if (WARN_ON(!mdp5_encoder->enabled))
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return;
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mdp5_ctl_set_encoder_state(ctl, pipeline, false);
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spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 0);
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spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
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mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf));
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/*
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* Wait for a vsync so we know the ENABLE=0 latched before
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* the (connector) source of the vsync's gets disabled,
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* otherwise we end up in a funny state if we re-enable
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* before the disable latches, which results that some of
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* the settings changes for the new modeset (like new
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* scanout buffer) don't latch properly..
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*/
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mdp_irq_wait(&mdp5_kms->base, intf2vblank(mixer, intf));
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bs_set(mdp5_encoder, 0);
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mdp5_encoder->enabled = false;
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}
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static void mdp5_vid_encoder_enable(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_kms *mdp5_kms = get_kms(encoder);
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struct mdp5_ctl *ctl = mdp5_encoder->ctl;
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struct mdp5_interface *intf = mdp5_encoder->intf;
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struct mdp5_pipeline *pipeline = mdp5_crtc_get_pipeline(encoder->crtc);
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int intfn = intf->num;
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unsigned long flags;
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if (WARN_ON(mdp5_encoder->enabled))
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return;
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bs_set(mdp5_encoder, 1);
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spin_lock_irqsave(&mdp5_encoder->intf_lock, flags);
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mdp5_write(mdp5_kms, REG_MDP5_INTF_TIMING_ENGINE_EN(intfn), 1);
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spin_unlock_irqrestore(&mdp5_encoder->intf_lock, flags);
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mdp5_ctl_commit(ctl, pipeline, mdp_ctl_flush_mask_encoder(intf));
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mdp5_ctl_set_encoder_state(ctl, pipeline, true);
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mdp5_encoder->enabled = true;
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}
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static void mdp5_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_interface *intf = mdp5_encoder->intf;
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if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)
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mdp5_cmd_encoder_mode_set(encoder, mode, adjusted_mode);
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else
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mdp5_vid_encoder_mode_set(encoder, mode, adjusted_mode);
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}
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static void mdp5_encoder_disable(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_interface *intf = mdp5_encoder->intf;
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if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)
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mdp5_cmd_encoder_disable(encoder);
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else
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mdp5_vid_encoder_disable(encoder);
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}
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static void mdp5_encoder_enable(struct drm_encoder *encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_interface *intf = mdp5_encoder->intf;
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/* this isn't right I think */
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struct drm_crtc_state *cstate = encoder->crtc->state;
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mdp5_encoder_mode_set(encoder, &cstate->mode, &cstate->adjusted_mode);
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if (intf->mode == MDP5_INTF_DSI_MODE_COMMAND)
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mdp5_cmd_encoder_enable(encoder);
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else
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mdp5_vid_encoder_enable(encoder);
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}
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static int mdp5_encoder_atomic_check(struct drm_encoder *encoder,
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struct drm_crtc_state *crtc_state,
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struct drm_connector_state *conn_state)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_crtc_state *mdp5_cstate = to_mdp5_crtc_state(crtc_state);
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struct mdp5_interface *intf = mdp5_encoder->intf;
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struct mdp5_ctl *ctl = mdp5_encoder->ctl;
|
||
|
|
|
||
|
|
mdp5_cstate->ctl = ctl;
|
||
|
|
mdp5_cstate->pipeline.intf = intf;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static const struct drm_encoder_helper_funcs mdp5_encoder_helper_funcs = {
|
||
|
|
.disable = mdp5_encoder_disable,
|
||
|
|
.enable = mdp5_encoder_enable,
|
||
|
|
.atomic_check = mdp5_encoder_atomic_check,
|
||
|
|
};
|
||
|
|
|
||
|
|
int mdp5_encoder_get_linecount(struct drm_encoder *encoder)
|
||
|
|
{
|
||
|
|
struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
|
||
|
|
struct mdp5_kms *mdp5_kms = get_kms(encoder);
|
||
|
|
int intf = mdp5_encoder->intf->num;
|
||
|
|
|
||
|
|
return mdp5_read(mdp5_kms, REG_MDP5_INTF_LINE_COUNT(intf));
|
||
|
|
}
|
||
|
|
|
||
|
|
u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder)
|
||
|
|
{
|
||
|
|
struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
|
||
|
|
struct mdp5_kms *mdp5_kms = get_kms(encoder);
|
||
|
|
int intf = mdp5_encoder->intf->num;
|
||
|
|
|
||
|
|
return mdp5_read(mdp5_kms, REG_MDP5_INTF_FRAME_COUNT(intf));
|
||
|
|
}
|
||
|
|
|
||
|
|
int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder,
|
||
|
|
struct drm_encoder *slave_encoder)
|
||
|
|
{
|
||
|
|
struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
|
||
|
|
struct mdp5_encoder *mdp5_slave_enc = to_mdp5_encoder(slave_encoder);
|
||
|
|
struct mdp5_kms *mdp5_kms;
|
||
|
|
struct device *dev;
|
||
|
|
int intf_num;
|
||
|
|
u32 data = 0;
|
||
|
|
|
||
|
|
if (!encoder || !slave_encoder)
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
mdp5_kms = get_kms(encoder);
|
||
|
|
intf_num = mdp5_encoder->intf->num;
|
||
|
|
|
||
|
|
/* Switch slave encoder's TimingGen Sync mode,
|
||
|
|
* to use the master's enable signal for the slave encoder.
|
||
|
|
*/
|
||
|
|
if (intf_num == 1)
|
||
|
|
data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC;
|
||
|
|
else if (intf_num == 2)
|
||
|
|
data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC;
|
||
|
|
else
|
||
|
|
return -EINVAL;
|
||
|
|
|
||
|
|
dev = &mdp5_kms->pdev->dev;
|
||
|
|
/* Make sure clocks are on when connectors calling this function. */
|
||
|
|
pm_runtime_get_sync(dev);
|
||
|
|
|
||
|
|
/* Dumb Panel, Sync mode */
|
||
|
|
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0);
|
||
|
|
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data);
|
||
|
|
mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1);
|
||
|
|
|
||
|
|
mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true);
|
||
|
|
|
||
|
|
pm_runtime_put_sync(dev);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode)
|
||
|
|
{
|
||
|
|
struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
|
||
|
|
struct mdp5_interface *intf = mdp5_encoder->intf;
|
||
|
|
|
||
|
|
/* TODO: Expand this to set writeback modes too */
|
||
|
|
if (cmd_mode) {
|
||
|
|
WARN_ON(intf->type != INTF_DSI);
|
||
|
|
intf->mode = MDP5_INTF_DSI_MODE_COMMAND;
|
||
|
|
} else {
|
||
|
|
if (intf->type == INTF_DSI)
|
||
|
|
intf->mode = MDP5_INTF_DSI_MODE_VIDEO;
|
||
|
|
else
|
||
|
|
intf->mode = MDP5_INTF_MODE_NONE;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/* initialize encoder */
|
||
|
|
struct drm_encoder *mdp5_encoder_init(struct drm_device *dev,
|
||
|
|
struct mdp5_interface *intf,
|
||
|
|
struct mdp5_ctl *ctl)
|
||
|
|
{
|
||
|
|
struct drm_encoder *encoder = NULL;
|
||
|
|
struct mdp5_encoder *mdp5_encoder;
|
||
|
|
int enc_type = (intf->type == INTF_DSI) ?
|
||
|
|
DRM_MODE_ENCODER_DSI : DRM_MODE_ENCODER_TMDS;
|
||
|
|
int ret;
|
||
|
|
|
||
|
|
mdp5_encoder = kzalloc(sizeof(*mdp5_encoder), GFP_KERNEL);
|
||
|
|
if (!mdp5_encoder) {
|
||
|
|
ret = -ENOMEM;
|
||
|
|
goto fail;
|
||
|
|
}
|
||
|
|
|
||
|
|
encoder = &mdp5_encoder->base;
|
||
|
|
mdp5_encoder->ctl = ctl;
|
||
|
|
mdp5_encoder->intf = intf;
|
||
|
|
|
||
|
|
spin_lock_init(&mdp5_encoder->intf_lock);
|
||
|
|
|
||
|
|
drm_encoder_init(dev, encoder, &mdp5_encoder_funcs, enc_type, NULL);
|
||
|
|
|
||
|
|
drm_encoder_helper_add(encoder, &mdp5_encoder_helper_funcs);
|
||
|
|
|
||
|
|
bs_init(mdp5_encoder);
|
||
|
|
|
||
|
|
return encoder;
|
||
|
|
|
||
|
|
fail:
|
||
|
|
if (encoder)
|
||
|
|
mdp5_encoder_destroy(encoder);
|
||
|
|
|
||
|
|
return ERR_PTR(ret);
|
||
|
|
}
|