395 lines
10 KiB
C
395 lines
10 KiB
C
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/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Ke Yu
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* Kevin Tian <kevin.tian@intel.com>
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* Dexuan Cui
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*
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* Contributors:
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* Tina Zhang <tina.zhang@intel.com>
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* Min He <min.he@intel.com>
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* Niu Bing <bing.niu@intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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*/
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#include "i915_drv.h"
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#include "gvt.h"
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/**
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* intel_vgpu_gpa_to_mmio_offset - translate a GPA to MMIO offset
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* @vgpu: a vGPU
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*
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* Returns:
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* Zero on success, negative error code if failed
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*/
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int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
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{
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u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
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return gpa - gttmmio_gpa;
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}
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#define reg_is_mmio(gvt, reg) \
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(reg >= 0 && reg < gvt->device_info.mmio_size)
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#define reg_is_gtt(gvt, reg) \
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(reg >= gvt->device_info.gtt_start_offset \
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&& reg < gvt->device_info.gtt_start_offset + gvt_ggtt_sz(gvt))
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static bool vgpu_gpa_is_aperture(struct intel_vgpu *vgpu, uint64_t gpa)
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{
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u64 aperture_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_2);
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u64 aperture_sz = vgpu_aperture_sz(vgpu);
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return gpa >= aperture_gpa && gpa < aperture_gpa + aperture_sz;
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}
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static int vgpu_aperture_rw(struct intel_vgpu *vgpu, uint64_t gpa,
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void *pdata, unsigned int size, bool is_read)
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{
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u64 aperture_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_2);
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u64 offset = gpa - aperture_gpa;
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if (!vgpu_gpa_is_aperture(vgpu, gpa + size - 1)) {
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gvt_vgpu_err("Aperture rw out of range, offset %llx, size %d\n",
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offset, size);
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return -EINVAL;
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}
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if (!vgpu->gm.aperture_va) {
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gvt_vgpu_err("BAR is not enabled\n");
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return -ENXIO;
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}
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if (is_read)
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memcpy(pdata, vgpu->gm.aperture_va + offset, size);
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else
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memcpy(vgpu->gm.aperture_va + offset, pdata, size);
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return 0;
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}
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static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, uint64_t pa,
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void *p_data, unsigned int bytes, bool read)
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{
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struct intel_gvt *gvt = NULL;
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void *pt = NULL;
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unsigned int offset = 0;
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if (!vgpu || !p_data)
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return;
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gvt = vgpu->gvt;
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mutex_lock(&gvt->lock);
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offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
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if (reg_is_mmio(gvt, offset)) {
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if (read)
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intel_vgpu_default_mmio_read(vgpu, offset, p_data,
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bytes);
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else
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intel_vgpu_default_mmio_write(vgpu, offset, p_data,
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bytes);
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} else if (reg_is_gtt(gvt, offset) &&
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vgpu->gtt.ggtt_mm->virtual_page_table) {
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offset -= gvt->device_info.gtt_start_offset;
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pt = vgpu->gtt.ggtt_mm->virtual_page_table + offset;
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if (read)
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memcpy(p_data, pt, bytes);
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else
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memcpy(pt, p_data, bytes);
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} else if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
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struct intel_vgpu_guest_page *gp;
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/* Since we enter the failsafe mode early during guest boot,
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* guest may not have chance to set up its ppgtt table, so
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* there should not be any wp pages for guest. Keep the wp
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* related code here in case we need to handle it in furture.
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*/
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gp = intel_vgpu_find_guest_page(vgpu, pa >> PAGE_SHIFT);
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if (gp) {
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/* remove write protection to prevent furture traps */
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intel_vgpu_clean_guest_page(vgpu, gp);
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if (read)
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intel_gvt_hypervisor_read_gpa(vgpu, pa,
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p_data, bytes);
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else
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intel_gvt_hypervisor_write_gpa(vgpu, pa,
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p_data, bytes);
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}
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}
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mutex_unlock(&gvt->lock);
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}
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/**
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* intel_vgpu_emulate_mmio_read - emulate MMIO read
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* @vgpu: a vGPU
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* @pa: guest physical address
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* @p_data: data return buffer
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* @bytes: access data length
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*
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* Returns:
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* Zero on success, negative error code if failed
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*/
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int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, uint64_t pa,
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void *p_data, unsigned int bytes)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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unsigned int offset = 0;
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int ret = -EINVAL;
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if (vgpu->failsafe) {
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failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);
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return 0;
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}
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mutex_lock(&gvt->lock);
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if (vgpu_gpa_is_aperture(vgpu, pa)) {
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ret = vgpu_aperture_rw(vgpu, pa, p_data, bytes, true);
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mutex_unlock(&gvt->lock);
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return ret;
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}
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if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
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struct intel_vgpu_guest_page *gp;
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gp = intel_vgpu_find_guest_page(vgpu, pa >> PAGE_SHIFT);
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if (gp) {
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ret = intel_gvt_hypervisor_read_gpa(vgpu, pa,
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p_data, bytes);
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if (ret) {
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gvt_vgpu_err("guest page read error %d, "
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"gfn 0x%lx, pa 0x%llx, var 0x%x, len %d\n",
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ret, gp->gfn, pa, *(u32 *)p_data,
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bytes);
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}
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mutex_unlock(&gvt->lock);
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return ret;
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}
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}
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offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
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if (WARN_ON(bytes > 8))
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goto err;
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if (reg_is_gtt(gvt, offset)) {
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if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
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goto err;
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if (WARN_ON(bytes != 4 && bytes != 8))
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goto err;
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if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
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goto err;
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ret = intel_vgpu_emulate_gtt_mmio_read(vgpu, offset,
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p_data, bytes);
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if (ret)
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goto err;
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mutex_unlock(&gvt->lock);
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return ret;
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}
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if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
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ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
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mutex_unlock(&gvt->lock);
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return ret;
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}
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if (WARN_ON(!reg_is_mmio(gvt, offset + bytes - 1)))
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goto err;
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if (!intel_gvt_mmio_is_unalign(gvt, offset)) {
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if (WARN_ON(!IS_ALIGNED(offset, bytes)))
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goto err;
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}
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ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);
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if (ret < 0)
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goto err;
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intel_gvt_mmio_set_accessed(gvt, offset);
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mutex_unlock(&gvt->lock);
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return 0;
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err:
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gvt_vgpu_err("fail to emulate MMIO read %08x len %d\n",
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offset, bytes);
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mutex_unlock(&gvt->lock);
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return ret;
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}
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/**
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* intel_vgpu_emulate_mmio_write - emulate MMIO write
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* @vgpu: a vGPU
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* @pa: guest physical address
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* @p_data: write data buffer
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* @bytes: access data length
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*
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* Returns:
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* Zero on success, negative error code if failed
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*/
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int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, uint64_t pa,
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void *p_data, unsigned int bytes)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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unsigned int offset = 0;
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int ret = -EINVAL;
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if (vgpu->failsafe) {
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failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);
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return 0;
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}
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mutex_lock(&gvt->lock);
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if (vgpu_gpa_is_aperture(vgpu, pa)) {
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ret = vgpu_aperture_rw(vgpu, pa, p_data, bytes, false);
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mutex_unlock(&gvt->lock);
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return ret;
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}
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if (atomic_read(&vgpu->gtt.n_write_protected_guest_page)) {
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struct intel_vgpu_guest_page *gp;
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gp = intel_vgpu_find_guest_page(vgpu, pa >> PAGE_SHIFT);
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if (gp) {
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ret = gp->handler(gp, pa, p_data, bytes);
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if (ret) {
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gvt_err("guest page write error %d, "
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"gfn 0x%lx, pa 0x%llx, "
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"var 0x%x, len %d\n",
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ret, gp->gfn, pa,
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*(u32 *)p_data, bytes);
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}
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mutex_unlock(&gvt->lock);
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return ret;
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}
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}
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offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
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if (WARN_ON(bytes > 8))
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goto err;
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if (reg_is_gtt(gvt, offset)) {
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if (WARN_ON(!IS_ALIGNED(offset, 4) && !IS_ALIGNED(offset, 8)))
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goto err;
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if (WARN_ON(bytes != 4 && bytes != 8))
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goto err;
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if (WARN_ON(!reg_is_gtt(gvt, offset + bytes - 1)))
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goto err;
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ret = intel_vgpu_emulate_gtt_mmio_write(vgpu, offset,
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p_data, bytes);
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if (ret)
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goto err;
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mutex_unlock(&gvt->lock);
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return ret;
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}
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if (WARN_ON_ONCE(!reg_is_mmio(gvt, offset))) {
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ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
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mutex_unlock(&gvt->lock);
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return ret;
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}
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ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
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if (ret < 0)
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goto err;
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intel_gvt_mmio_set_accessed(gvt, offset);
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mutex_unlock(&gvt->lock);
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return 0;
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err:
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gvt_vgpu_err("fail to emulate MMIO write %08x len %d\n", offset,
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bytes);
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mutex_unlock(&gvt->lock);
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return ret;
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}
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/**
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* intel_vgpu_reset_mmio - reset virtual MMIO space
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* @vgpu: a vGPU
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*
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*/
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void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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const struct intel_gvt_device_info *info = &gvt->device_info;
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void *mmio = gvt->firmware.mmio;
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if (dmlr) {
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memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
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memcpy(vgpu->mmio.sreg, mmio, info->mmio_size);
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vgpu_vreg(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
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/* set the bit 0:2(Core C-State ) to C0 */
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vgpu_vreg(vgpu, GEN6_GT_CORE_STATUS) = 0;
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vgpu->mmio.disable_warn_untrack = false;
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} else {
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#define GVT_GEN8_MMIO_RESET_OFFSET (0x44200)
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/* only reset the engine related, so starting with 0x44200
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* interrupt include DE,display mmio related will not be
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* touched
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*/
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|
memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
|
||
|
|
memcpy(vgpu->mmio.sreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* intel_vgpu_init_mmio - init MMIO space
|
||
|
|
* @vgpu: a vGPU
|
||
|
|
*
|
||
|
|
* Returns:
|
||
|
|
* Zero on success, negative error code if failed
|
||
|
|
*/
|
||
|
|
int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
|
||
|
|
{
|
||
|
|
const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
|
||
|
|
|
||
|
|
vgpu->mmio.vreg = vzalloc(info->mmio_size * 2);
|
||
|
|
if (!vgpu->mmio.vreg)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
vgpu->mmio.sreg = vgpu->mmio.vreg + info->mmio_size;
|
||
|
|
|
||
|
|
intel_vgpu_reset_mmio(vgpu, true);
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* intel_vgpu_clean_mmio - clean MMIO space
|
||
|
|
* @vgpu: a vGPU
|
||
|
|
*
|
||
|
|
*/
|
||
|
|
void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
|
||
|
|
{
|
||
|
|
vfree(vgpu->mmio.vreg);
|
||
|
|
vgpu->mmio.vreg = vgpu->mmio.sreg = NULL;
|
||
|
|
}
|