231 lines
5.0 KiB
C
231 lines
5.0 KiB
C
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/*
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* Copyright (c) 2016 Linaro Limited.
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* Copyright (c) 2014-2016 Hisilicon Limited.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#ifndef __KIRIN_ADE_REG_H__
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#define __KIRIN_ADE_REG_H__
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/*
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* ADE Registers
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*/
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#define MASK(x) (BIT(x) - 1)
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#define ADE_CTRL 0x0004
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#define FRM_END_START_OFST 0
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#define FRM_END_START_MASK MASK(2)
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#define AUTO_CLK_GATE_EN_OFST 0
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#define AUTO_CLK_GATE_EN BIT(0)
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#define ADE_DISP_SRC_CFG 0x0018
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#define ADE_CTRL1 0x008C
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#define ADE_EN 0x0100
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#define ADE_DISABLE 0
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#define ADE_ENABLE 1
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/* reset and reload regs */
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#define ADE_SOFT_RST_SEL(x) (0x0078 + (x) * 0x4)
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#define ADE_RELOAD_DIS(x) (0x00AC + (x) * 0x4)
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#define RDMA_OFST 0
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#define CLIP_OFST 15
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#define SCL_OFST 21
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#define CTRAN_OFST 24
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#define OVLY_OFST 37 /* 32+5 */
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/* channel regs */
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#define RD_CH_CTRL(x) (0x1004 + (x) * 0x80)
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#define RD_CH_ADDR(x) (0x1008 + (x) * 0x80)
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#define RD_CH_SIZE(x) (0x100C + (x) * 0x80)
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#define RD_CH_STRIDE(x) (0x1010 + (x) * 0x80)
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#define RD_CH_SPACE(x) (0x1014 + (x) * 0x80)
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#define RD_CH_EN(x) (0x1020 + (x) * 0x80)
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/* overlay regs */
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#define ADE_OVLY1_TRANS_CFG 0x002C
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#define ADE_OVLY_CTL 0x0098
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#define ADE_OVLY_CH_XY0(x) (0x2004 + (x) * 4)
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#define ADE_OVLY_CH_XY1(x) (0x2024 + (x) * 4)
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#define ADE_OVLY_CH_CTL(x) (0x204C + (x) * 4)
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#define ADE_OVLY_OUTPUT_SIZE(x) (0x2070 + (x) * 8)
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#define OUTPUT_XSIZE_OFST 16
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#define ADE_OVLYX_CTL(x) (0x209C + (x) * 4)
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#define CH_OVLY_SEL_OFST(x) ((x) * 4)
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#define CH_OVLY_SEL_MASK MASK(2)
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#define CH_OVLY_SEL_VAL(x) ((x) + 1)
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#define CH_ALP_MODE_OFST 0
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#define CH_ALP_SEL_OFST 2
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#define CH_UNDER_ALP_SEL_OFST 4
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#define CH_EN_OFST 6
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#define CH_ALP_GBL_OFST 15
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#define CH_SEL_OFST 28
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/* ctran regs */
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#define ADE_CTRAN_DIS(x) (0x5004 + (x) * 0x100)
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#define CTRAN_BYPASS_ON 1
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#define CTRAN_BYPASS_OFF 0
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#define ADE_CTRAN_IMAGE_SIZE(x) (0x503C + (x) * 0x100)
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/* clip regs */
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#define ADE_CLIP_DISABLE(x) (0x6800 + (x) * 0x100)
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#define ADE_CLIP_SIZE0(x) (0x6804 + (x) * 0x100)
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#define ADE_CLIP_SIZE1(x) (0x6808 + (x) * 0x100)
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/*
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* LDI Registers
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*/
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#define LDI_HRZ_CTRL0 0x7400
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#define HBP_OFST 20
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#define LDI_HRZ_CTRL1 0x7404
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#define LDI_VRT_CTRL0 0x7408
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#define VBP_OFST 20
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#define LDI_VRT_CTRL1 0x740C
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#define LDI_PLR_CTRL 0x7410
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#define FLAG_NVSYNC BIT(0)
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#define FLAG_NHSYNC BIT(1)
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#define FLAG_NPIXCLK BIT(2)
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#define FLAG_NDE BIT(3)
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#define LDI_DSP_SIZE 0x7414
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#define VSIZE_OFST 20
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#define LDI_INT_EN 0x741C
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#define FRAME_END_INT_EN_OFST 1
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#define LDI_CTRL 0x7420
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#define BPP_OFST 3
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#define DATA_GATE_EN BIT(2)
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#define LDI_EN BIT(0)
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#define LDI_MSK_INT 0x7428
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#define LDI_INT_CLR 0x742C
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#define LDI_WORK_MODE 0x7430
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#define LDI_HDMI_DSI_GT 0x7434
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/*
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* ADE media bus service regs
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*/
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#define ADE0_QOSGENERATOR_MODE 0x010C
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#define QOSGENERATOR_MODE_MASK MASK(2)
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#define ADE0_QOSGENERATOR_EXTCONTROL 0x0118
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#define SOCKET_QOS_EN BIT(0)
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#define ADE1_QOSGENERATOR_MODE 0x020C
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#define ADE1_QOSGENERATOR_EXTCONTROL 0x0218
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/*
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* ADE regs relevant enums
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*/
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enum frame_end_start {
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/* regs take effect in every vsync */
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REG_EFFECTIVE_IN_VSYNC = 0,
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/* regs take effect in fist ade en and every frame end */
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REG_EFFECTIVE_IN_ADEEN_FRMEND,
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/* regs take effect in ade en immediately */
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REG_EFFECTIVE_IN_ADEEN,
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/* regs take effect in first vsync and every frame end */
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REG_EFFECTIVE_IN_VSYNC_FRMEND
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};
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enum ade_fb_format {
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ADE_RGB_565 = 0,
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ADE_BGR_565,
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ADE_XRGB_8888,
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ADE_XBGR_8888,
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ADE_ARGB_8888,
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ADE_ABGR_8888,
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ADE_RGBA_8888,
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ADE_BGRA_8888,
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ADE_RGB_888,
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ADE_BGR_888 = 9,
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ADE_FORMAT_UNSUPPORT = 800
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};
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enum ade_channel {
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ADE_CH1 = 0, /* channel 1 for primary plane */
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ADE_CH_NUM
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};
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enum ade_scale {
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ADE_SCL1 = 0,
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ADE_SCL2,
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ADE_SCL3,
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ADE_SCL_NUM
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};
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enum ade_ctran {
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ADE_CTRAN1 = 0,
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ADE_CTRAN2,
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ADE_CTRAN3,
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ADE_CTRAN4,
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ADE_CTRAN5,
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ADE_CTRAN6,
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ADE_CTRAN_NUM
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};
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enum ade_overlay {
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ADE_OVLY1 = 0,
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ADE_OVLY2,
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ADE_OVLY3,
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ADE_OVLY_NUM
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};
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enum ade_alpha_mode {
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ADE_ALP_GLOBAL = 0,
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ADE_ALP_PIXEL,
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ADE_ALP_PIXEL_AND_GLB
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};
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enum ade_alpha_blending_mode {
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ADE_ALP_MUL_COEFF_0 = 0, /* alpha */
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ADE_ALP_MUL_COEFF_1, /* 1-alpha */
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ADE_ALP_MUL_COEFF_2, /* 0 */
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ADE_ALP_MUL_COEFF_3 /* 1 */
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};
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/*
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* LDI regs relevant enums
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*/
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enum dsi_pclk_en {
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DSI_PCLK_ON = 0,
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DSI_PCLK_OFF
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};
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enum ldi_output_format {
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LDI_OUT_RGB_565 = 0,
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LDI_OUT_RGB_666,
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LDI_OUT_RGB_888
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};
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enum ldi_work_mode {
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TEST_MODE = 0,
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NORMAL_MODE
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};
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enum ldi_input_source {
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DISP_SRC_NONE = 0,
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DISP_SRC_OVLY2,
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DISP_SRC_DISP,
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DISP_SRC_ROT,
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DISP_SRC_SCL2
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};
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/*
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* ADE media bus service relevant enums
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*/
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enum qos_generator_mode {
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FIXED_MODE = 0,
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LIMITER_MODE,
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BYPASS_MODE,
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REGULATOR_MODE
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};
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/*
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* Register Write/Read Helper functions
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*/
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static inline void ade_update_bits(void __iomem *addr, u32 bit_start,
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u32 mask, u32 val)
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{
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u32 tmp, orig;
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orig = readl(addr);
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tmp = orig & ~(mask << bit_start);
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tmp |= (val & mask) << bit_start;
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writel(tmp, addr);
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}
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#endif
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