328 lines
8.1 KiB
C
328 lines
8.1 KiB
C
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/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Li Peng <peng.li@intel.com>
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*/
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#include <linux/export.h>
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#include <linux/mutex.h>
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#include <linux/pci.h>
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#include <linux/i2c.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include "psb_drv.h"
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#define HDMI_READ(reg) readl(hdmi_dev->regs + (reg))
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#define HDMI_WRITE(reg, val) writel(val, hdmi_dev->regs + (reg))
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#define HDMI_HCR 0x1000
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#define HCR_DETECT_HDP (1 << 6)
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#define HCR_ENABLE_HDCP (1 << 5)
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#define HCR_ENABLE_AUDIO (1 << 2)
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#define HCR_ENABLE_PIXEL (1 << 1)
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#define HCR_ENABLE_TMDS (1 << 0)
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#define HDMI_HICR 0x1004
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#define HDMI_INTR_I2C_ERROR (1 << 4)
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#define HDMI_INTR_I2C_FULL (1 << 3)
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#define HDMI_INTR_I2C_DONE (1 << 2)
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#define HDMI_INTR_HPD (1 << 0)
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#define HDMI_HSR 0x1008
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#define HDMI_HISR 0x100C
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#define HDMI_HI2CRDB0 0x1200
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#define HDMI_HI2CHCR 0x1240
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#define HI2C_HDCP_WRITE (0 << 2)
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#define HI2C_HDCP_RI_READ (1 << 2)
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#define HI2C_HDCP_READ (2 << 2)
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#define HI2C_EDID_READ (3 << 2)
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#define HI2C_READ_CONTINUE (1 << 1)
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#define HI2C_ENABLE_TRANSACTION (1 << 0)
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#define HDMI_ICRH 0x1100
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#define HDMI_HI2CTDR0 0x1244
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#define HDMI_HI2CTDR1 0x1248
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#define I2C_STAT_INIT 0
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#define I2C_READ_DONE 1
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#define I2C_TRANSACTION_DONE 2
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struct hdmi_i2c_dev {
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struct i2c_adapter *adap;
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struct mutex i2c_lock;
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struct completion complete;
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int status;
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struct i2c_msg *msg;
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int buf_offset;
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};
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static void hdmi_i2c_irq_enable(struct oaktrail_hdmi_dev *hdmi_dev)
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{
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u32 temp;
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temp = HDMI_READ(HDMI_HICR);
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temp |= (HDMI_INTR_I2C_ERROR | HDMI_INTR_I2C_FULL | HDMI_INTR_I2C_DONE);
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HDMI_WRITE(HDMI_HICR, temp);
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HDMI_READ(HDMI_HICR);
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}
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static void hdmi_i2c_irq_disable(struct oaktrail_hdmi_dev *hdmi_dev)
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{
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HDMI_WRITE(HDMI_HICR, 0x0);
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HDMI_READ(HDMI_HICR);
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}
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static int xfer_read(struct i2c_adapter *adap, struct i2c_msg *pmsg)
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{
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struct oaktrail_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap);
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struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
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u32 temp;
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i2c_dev->status = I2C_STAT_INIT;
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i2c_dev->msg = pmsg;
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i2c_dev->buf_offset = 0;
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reinit_completion(&i2c_dev->complete);
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/* Enable I2C transaction */
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temp = ((pmsg->len) << 20) | HI2C_EDID_READ | HI2C_ENABLE_TRANSACTION;
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HDMI_WRITE(HDMI_HI2CHCR, temp);
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HDMI_READ(HDMI_HI2CHCR);
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while (i2c_dev->status != I2C_TRANSACTION_DONE)
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wait_for_completion_interruptible_timeout(&i2c_dev->complete,
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10 * HZ);
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return 0;
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}
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static int xfer_write(struct i2c_adapter *adap, struct i2c_msg *pmsg)
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{
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/*
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* XXX: i2c write seems isn't useful for EDID probe, don't do anything
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*/
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return 0;
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}
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static int oaktrail_hdmi_i2c_access(struct i2c_adapter *adap,
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struct i2c_msg *pmsg,
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int num)
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{
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struct oaktrail_hdmi_dev *hdmi_dev = i2c_get_adapdata(adap);
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struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
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int i;
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mutex_lock(&i2c_dev->i2c_lock);
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/* Enable i2c unit */
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HDMI_WRITE(HDMI_ICRH, 0x00008760);
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/* Enable irq */
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hdmi_i2c_irq_enable(hdmi_dev);
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for (i = 0; i < num; i++) {
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if (pmsg->len && pmsg->buf) {
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if (pmsg->flags & I2C_M_RD)
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xfer_read(adap, pmsg);
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else
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xfer_write(adap, pmsg);
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}
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pmsg++; /* next message */
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}
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/* Disable irq */
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hdmi_i2c_irq_disable(hdmi_dev);
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mutex_unlock(&i2c_dev->i2c_lock);
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return i;
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}
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static u32 oaktrail_hdmi_i2c_func(struct i2c_adapter *adapter)
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{
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return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
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}
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static const struct i2c_algorithm oaktrail_hdmi_i2c_algorithm = {
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.master_xfer = oaktrail_hdmi_i2c_access,
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.functionality = oaktrail_hdmi_i2c_func,
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};
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static struct i2c_adapter oaktrail_hdmi_i2c_adapter = {
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.name = "oaktrail_hdmi_i2c",
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.nr = 3,
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.owner = THIS_MODULE,
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.class = I2C_CLASS_DDC,
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.algo = &oaktrail_hdmi_i2c_algorithm,
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};
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static void hdmi_i2c_read(struct oaktrail_hdmi_dev *hdmi_dev)
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{
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struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
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struct i2c_msg *msg = i2c_dev->msg;
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u8 *buf = msg->buf;
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u32 temp;
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int i, offset;
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offset = i2c_dev->buf_offset;
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for (i = 0; i < 0x10; i++) {
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temp = HDMI_READ(HDMI_HI2CRDB0 + (i * 4));
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memcpy(buf + (offset + i * 4), &temp, 4);
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}
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i2c_dev->buf_offset += (0x10 * 4);
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/* clearing read buffer full intr */
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temp = HDMI_READ(HDMI_HISR);
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HDMI_WRITE(HDMI_HISR, temp | HDMI_INTR_I2C_FULL);
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HDMI_READ(HDMI_HISR);
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/* continue read transaction */
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temp = HDMI_READ(HDMI_HI2CHCR);
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HDMI_WRITE(HDMI_HI2CHCR, temp | HI2C_READ_CONTINUE);
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HDMI_READ(HDMI_HI2CHCR);
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i2c_dev->status = I2C_READ_DONE;
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return;
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}
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static void hdmi_i2c_transaction_done(struct oaktrail_hdmi_dev *hdmi_dev)
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{
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struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
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u32 temp;
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/* clear transaction done intr */
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temp = HDMI_READ(HDMI_HISR);
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HDMI_WRITE(HDMI_HISR, temp | HDMI_INTR_I2C_DONE);
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HDMI_READ(HDMI_HISR);
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temp = HDMI_READ(HDMI_HI2CHCR);
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HDMI_WRITE(HDMI_HI2CHCR, temp & ~HI2C_ENABLE_TRANSACTION);
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HDMI_READ(HDMI_HI2CHCR);
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i2c_dev->status = I2C_TRANSACTION_DONE;
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return;
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}
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static irqreturn_t oaktrail_hdmi_i2c_handler(int this_irq, void *dev)
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{
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struct oaktrail_hdmi_dev *hdmi_dev = dev;
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struct hdmi_i2c_dev *i2c_dev = hdmi_dev->i2c_dev;
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u32 stat;
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stat = HDMI_READ(HDMI_HISR);
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if (stat & HDMI_INTR_HPD) {
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HDMI_WRITE(HDMI_HISR, stat | HDMI_INTR_HPD);
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HDMI_READ(HDMI_HISR);
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}
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if (stat & HDMI_INTR_I2C_FULL)
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hdmi_i2c_read(hdmi_dev);
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if (stat & HDMI_INTR_I2C_DONE)
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hdmi_i2c_transaction_done(hdmi_dev);
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complete(&i2c_dev->complete);
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return IRQ_HANDLED;
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}
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/*
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* choose alternate function 2 of GPIO pin 52, 53,
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* which is used by HDMI I2C logic
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*/
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static void oaktrail_hdmi_i2c_gpio_fix(void)
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{
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void __iomem *base;
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unsigned int gpio_base = 0xff12c000;
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int gpio_len = 0x1000;
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u32 temp;
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base = ioremap((resource_size_t)gpio_base, gpio_len);
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if (base == NULL) {
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DRM_ERROR("gpio ioremap fail\n");
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return;
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}
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temp = readl(base + 0x44);
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DRM_DEBUG_DRIVER("old gpio val %x\n", temp);
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writel((temp | 0x00000a00), (base + 0x44));
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temp = readl(base + 0x44);
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DRM_DEBUG_DRIVER("new gpio val %x\n", temp);
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iounmap(base);
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}
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int oaktrail_hdmi_i2c_init(struct pci_dev *dev)
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{
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struct oaktrail_hdmi_dev *hdmi_dev;
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struct hdmi_i2c_dev *i2c_dev;
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int ret;
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hdmi_dev = pci_get_drvdata(dev);
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i2c_dev = kzalloc(sizeof(struct hdmi_i2c_dev), GFP_KERNEL);
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if (i2c_dev == NULL) {
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DRM_ERROR("Can't allocate interface\n");
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ret = -ENOMEM;
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goto exit;
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}
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i2c_dev->adap = &oaktrail_hdmi_i2c_adapter;
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i2c_dev->status = I2C_STAT_INIT;
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init_completion(&i2c_dev->complete);
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mutex_init(&i2c_dev->i2c_lock);
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i2c_set_adapdata(&oaktrail_hdmi_i2c_adapter, hdmi_dev);
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hdmi_dev->i2c_dev = i2c_dev;
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/* Enable HDMI I2C function on gpio */
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oaktrail_hdmi_i2c_gpio_fix();
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/* request irq */
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ret = request_irq(dev->irq, oaktrail_hdmi_i2c_handler, IRQF_SHARED,
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oaktrail_hdmi_i2c_adapter.name, hdmi_dev);
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if (ret) {
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DRM_ERROR("Failed to request IRQ for I2C controller\n");
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goto err;
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}
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/* Adapter registration */
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ret = i2c_add_numbered_adapter(&oaktrail_hdmi_i2c_adapter);
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return ret;
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err:
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kfree(i2c_dev);
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exit:
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return ret;
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}
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void oaktrail_hdmi_i2c_exit(struct pci_dev *dev)
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{
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struct oaktrail_hdmi_dev *hdmi_dev;
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struct hdmi_i2c_dev *i2c_dev;
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hdmi_dev = pci_get_drvdata(dev);
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i2c_del_adapter(&oaktrail_hdmi_i2c_adapter);
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i2c_dev = hdmi_dev->i2c_dev;
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kfree(i2c_dev);
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free_irq(dev->irq, hdmi_dev);
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}
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