511 lines
14 KiB
C
511 lines
14 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU71_H
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#define SMU71_H
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#if !defined(SMC_MICROCODE)
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#pragma pack(push, 1)
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#endif
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#define SMU__NUM_PCIE_DPM_LEVELS 8
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#define SMU__NUM_SCLK_DPM_STATE 8
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#define SMU__NUM_MCLK_DPM_LEVELS 4
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#define SMU__VARIANT__ICELAND 1
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#define SMU__DGPU_ONLY 1
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#define SMU__DYNAMIC_MCARB_SETTINGS 1
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enum SID_OPTION {
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SID_OPTION_HI,
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SID_OPTION_LO,
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SID_OPTION_COUNT
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};
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typedef struct {
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uint32_t high;
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uint32_t low;
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} data_64_t;
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typedef struct {
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data_64_t high;
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data_64_t low;
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} data_128_t;
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#define SMU7_CONTEXT_ID_SMC 1
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#define SMU7_CONTEXT_ID_VBIOS 2
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#define SMU71_MAX_LEVELS_VDDC 8
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#define SMU71_MAX_LEVELS_VDDCI 4
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#define SMU71_MAX_LEVELS_MVDD 4
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#define SMU71_MAX_LEVELS_VDDNB 8
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#define SMU71_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE
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#define SMU71_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS
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#define SMU71_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS
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#define SMU71_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS
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#define SMU71_MAX_ENTRIES_SMIO 32
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#define DPM_NO_LIMIT 0
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#define DPM_NO_UP 1
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#define DPM_GO_DOWN 2
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#define DPM_GO_UP 3
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#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
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#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
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#define GPIO_CLAMP_MODE_VRHOT 1
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#define GPIO_CLAMP_MODE_THERM 2
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#define GPIO_CLAMP_MODE_DC 4
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#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
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#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
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#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
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#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
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#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
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#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
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#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
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#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
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#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
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#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
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#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
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#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
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#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
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#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
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#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
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#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
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#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
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#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
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#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
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#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
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#if defined SMU__DGPU_ONLY
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#define SMU71_DTE_ITERATIONS 5
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#define SMU71_DTE_SOURCES 3
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#define SMU71_DTE_SINKS 1
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#define SMU71_NUM_CPU_TES 0
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#define SMU71_NUM_GPU_TES 1
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#define SMU71_NUM_NON_TES 2
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#endif
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#if defined SMU__FUSION_ONLY
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#define SMU7_DTE_ITERATIONS 5
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#define SMU7_DTE_SOURCES 5
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#define SMU7_DTE_SINKS 3
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#define SMU7_NUM_CPU_TES 2
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#define SMU7_NUM_GPU_TES 1
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#define SMU7_NUM_NON_TES 2
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#endif
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struct SMU71_PIDController
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{
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uint32_t Ki;
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int32_t LFWindupUpperLim;
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int32_t LFWindupLowerLim;
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uint32_t StatePrecision;
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uint32_t LfPrecision;
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uint32_t LfOffset;
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uint32_t MaxState;
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uint32_t MaxLfFraction;
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uint32_t StateShift;
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};
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typedef struct SMU71_PIDController SMU71_PIDController;
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struct SMU7_LocalDpmScoreboard
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{
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uint32_t PercentageBusy;
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int32_t PIDError;
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int32_t PIDIntegral;
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int32_t PIDOutput;
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uint32_t SigmaDeltaAccum;
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uint32_t SigmaDeltaOutput;
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uint32_t SigmaDeltaLevel;
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uint32_t UtilizationSetpoint;
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uint8_t TdpClampMode;
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uint8_t TdcClampMode;
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uint8_t ThermClampMode;
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uint8_t VoltageBusy;
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int8_t CurrLevel;
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int8_t TargLevel;
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uint8_t LevelChangeInProgress;
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uint8_t UpHyst;
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uint8_t DownHyst;
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uint8_t VoltageDownHyst;
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uint8_t DpmEnable;
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uint8_t DpmRunning;
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uint8_t DpmForce;
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uint8_t DpmForceLevel;
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uint8_t DisplayWatermark;
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uint8_t McArbIndex;
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uint32_t MinimumPerfSclk;
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uint8_t AcpiReq;
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uint8_t AcpiAck;
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uint8_t GfxClkSlow;
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uint8_t GpioClampMode;
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uint8_t FpsFilterWeight;
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uint8_t EnabledLevelsChange;
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uint8_t DteClampMode;
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uint8_t FpsClampMode;
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uint16_t LevelResidencyCounters [SMU71_MAX_LEVELS_GRAPHICS];
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uint16_t LevelSwitchCounters [SMU71_MAX_LEVELS_GRAPHICS];
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void (*TargetStateCalculator)(uint8_t);
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void (*SavedTargetStateCalculator)(uint8_t);
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uint16_t AutoDpmInterval;
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uint16_t AutoDpmRange;
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uint8_t FpsEnabled;
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uint8_t MaxPerfLevel;
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uint8_t AllowLowClkInterruptToHost;
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uint8_t FpsRunning;
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uint32_t MaxAllowedFrequency;
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};
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typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
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#define SMU7_MAX_VOLTAGE_CLIENTS 12
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struct SMU7_VoltageScoreboard
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{
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uint16_t CurrentVoltage;
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uint16_t HighestVoltage;
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uint16_t MaxVid;
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uint8_t HighestVidOffset;
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uint8_t CurrentVidOffset;
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#if defined (SMU__DGPU_ONLY)
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uint8_t CurrentPhases;
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uint8_t HighestPhases;
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#else
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uint8_t AvsOffset;
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uint8_t AvsOffsetApplied;
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#endif
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uint8_t ControllerBusy;
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uint8_t CurrentVid;
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uint16_t RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
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#if defined (SMU__DGPU_ONLY)
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uint8_t RequestedPhases[SMU7_MAX_VOLTAGE_CLIENTS];
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#endif
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uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
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uint8_t TargetIndex;
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uint8_t Delay;
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uint8_t ControllerEnable;
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uint8_t ControllerRunning;
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uint16_t CurrentStdVoltageHiSidd;
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uint16_t CurrentStdVoltageLoSidd;
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#if defined (SMU__DGPU_ONLY)
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uint16_t RequestedVddci;
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uint16_t CurrentVddci;
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uint16_t HighestVddci;
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uint8_t CurrentVddciVid;
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uint8_t TargetVddciIndex;
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#endif
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};
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typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
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// -------------------------------------------------------------------------------------------------------------------------
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#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
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struct SMU7_PCIeLinkSpeedScoreboard
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{
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uint8_t DpmEnable;
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uint8_t DpmRunning;
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uint8_t DpmForce;
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uint8_t DpmForceLevel;
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uint8_t CurrentLinkSpeed;
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uint8_t EnabledLevelsChange;
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uint16_t AutoDpmInterval;
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uint16_t AutoDpmRange;
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uint16_t AutoDpmCount;
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uint8_t DpmMode;
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uint8_t AcpiReq;
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uint8_t AcpiAck;
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uint8_t CurrentLinkLevel;
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};
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typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
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// -------------------------------------------------------- CAC table ------------------------------------------------------
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#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
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#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
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#define SMU7_SCALE_I 7
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#define SMU7_SCALE_R 12
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struct SMU7_PowerScoreboard
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{
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uint16_t MinVoltage;
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uint16_t MaxVoltage;
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uint32_t AvgGpuPower;
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uint16_t VddcLeakagePower[SID_OPTION_COUNT];
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uint16_t VddcSclkConstantPower[SID_OPTION_COUNT];
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uint16_t VddcSclkDynamicPower[SID_OPTION_COUNT];
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uint16_t VddcNonSclkDynamicPower[SID_OPTION_COUNT];
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uint16_t VddcTotalPower[SID_OPTION_COUNT];
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uint16_t VddcTotalCurrent[SID_OPTION_COUNT];
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uint16_t VddcLoadVoltage[SID_OPTION_COUNT];
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uint16_t VddcNoLoadVoltage[SID_OPTION_COUNT];
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uint16_t DisplayPhyPower;
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uint16_t PciePhyPower;
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uint16_t VddciTotalPower;
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uint16_t Vddr1TotalPower;
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uint32_t RocPower;
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uint32_t last_power;
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uint32_t enableWinAvg;
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uint32_t lkg_acc;
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uint16_t VoltLkgeScaler;
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uint16_t TempLkgeScaler;
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uint32_t uvd_cac_dclk;
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uint32_t uvd_cac_vclk;
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uint32_t vce_cac_eclk;
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uint32_t samu_cac_samclk;
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uint32_t display_cac_dispclk;
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uint32_t acp_cac_aclk;
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uint32_t unb_cac;
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uint32_t WinTime;
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uint16_t GpuPwr_MAWt;
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uint16_t FilteredVddcTotalPower;
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uint8_t CalculationRepeats;
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uint8_t WaterfallUp;
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uint8_t WaterfallDown;
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uint8_t WaterfallLimit;
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};
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typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
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// --------------------------------------------------------------------------------------------------
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struct SMU7_ThermalScoreboard
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{
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int16_t GpuLimit;
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int16_t GpuHyst;
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uint16_t CurrGnbTemp;
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uint16_t FilteredGnbTemp;
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uint8_t ControllerEnable;
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uint8_t ControllerRunning;
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uint8_t WaterfallUp;
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uint8_t WaterfallDown;
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uint8_t WaterfallLimit;
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uint8_t padding[3];
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};
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typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
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// For FeatureEnables:
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#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
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#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
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#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
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#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
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#define SMU7_UVD_DPM_CONFIG_MASK 0x10
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#define SMU7_VCE_DPM_CONFIG_MASK 0x20
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#define SMU7_ACP_DPM_CONFIG_MASK 0x40
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#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
|
||
|
|
#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
|
||
|
|
|
||
|
|
#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
|
||
|
|
#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
|
||
|
|
#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
|
||
|
|
#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
|
||
|
|
#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
|
||
|
|
#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
|
||
|
|
|
||
|
|
// All 'soft registers' should be uint32_t.
|
||
|
|
struct SMU71_SoftRegisters
|
||
|
|
{
|
||
|
|
uint32_t RefClockFrequency;
|
||
|
|
uint32_t PmTimerPeriod;
|
||
|
|
uint32_t FeatureEnables;
|
||
|
|
#if defined (SMU__DGPU_ONLY)
|
||
|
|
uint32_t PreVBlankGap;
|
||
|
|
uint32_t VBlankTimeout;
|
||
|
|
uint32_t TrainTimeGap;
|
||
|
|
uint32_t MvddSwitchTime;
|
||
|
|
uint32_t LongestAcpiTrainTime;
|
||
|
|
uint32_t AcpiDelay;
|
||
|
|
uint32_t G5TrainTime;
|
||
|
|
uint32_t DelayMpllPwron;
|
||
|
|
uint32_t VoltageChangeTimeout;
|
||
|
|
#endif
|
||
|
|
uint32_t HandshakeDisables;
|
||
|
|
|
||
|
|
uint8_t DisplayPhy1Config;
|
||
|
|
uint8_t DisplayPhy2Config;
|
||
|
|
uint8_t DisplayPhy3Config;
|
||
|
|
uint8_t DisplayPhy4Config;
|
||
|
|
|
||
|
|
uint8_t DisplayPhy5Config;
|
||
|
|
uint8_t DisplayPhy6Config;
|
||
|
|
uint8_t DisplayPhy7Config;
|
||
|
|
uint8_t DisplayPhy8Config;
|
||
|
|
|
||
|
|
uint32_t AverageGraphicsActivity;
|
||
|
|
uint32_t AverageMemoryActivity;
|
||
|
|
uint32_t AverageGioActivity;
|
||
|
|
|
||
|
|
uint8_t SClkDpmEnabledLevels;
|
||
|
|
uint8_t MClkDpmEnabledLevels;
|
||
|
|
uint8_t LClkDpmEnabledLevels;
|
||
|
|
uint8_t PCIeDpmEnabledLevels;
|
||
|
|
|
||
|
|
uint32_t DRAM_LOG_ADDR_H;
|
||
|
|
uint32_t DRAM_LOG_ADDR_L;
|
||
|
|
uint32_t DRAM_LOG_PHY_ADDR_H;
|
||
|
|
uint32_t DRAM_LOG_PHY_ADDR_L;
|
||
|
|
uint32_t DRAM_LOG_BUFF_SIZE;
|
||
|
|
uint32_t UlvEnterCount;
|
||
|
|
uint32_t UlvTime;
|
||
|
|
uint32_t UcodeLoadStatus;
|
||
|
|
uint8_t DPMFreezeAndForced;
|
||
|
|
uint8_t Activity_Weight;
|
||
|
|
uint8_t Reserved8[2];
|
||
|
|
uint32_t Reserved;
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU71_SoftRegisters SMU71_SoftRegisters;
|
||
|
|
|
||
|
|
struct SMU71_Firmware_Header
|
||
|
|
{
|
||
|
|
uint32_t Digest[5];
|
||
|
|
uint32_t Version;
|
||
|
|
uint32_t HeaderSize;
|
||
|
|
uint32_t Flags;
|
||
|
|
uint32_t EntryPoint;
|
||
|
|
uint32_t CodeSize;
|
||
|
|
uint32_t ImageSize;
|
||
|
|
|
||
|
|
uint32_t Rtos;
|
||
|
|
uint32_t SoftRegisters;
|
||
|
|
uint32_t DpmTable;
|
||
|
|
uint32_t FanTable;
|
||
|
|
uint32_t CacConfigTable;
|
||
|
|
uint32_t CacStatusTable;
|
||
|
|
|
||
|
|
uint32_t mcRegisterTable;
|
||
|
|
|
||
|
|
uint32_t mcArbDramTimingTable;
|
||
|
|
|
||
|
|
uint32_t PmFuseTable;
|
||
|
|
uint32_t Globals;
|
||
|
|
uint32_t UvdDpmTable;
|
||
|
|
uint32_t AcpDpmTable;
|
||
|
|
uint32_t VceDpmTable;
|
||
|
|
uint32_t SamuDpmTable;
|
||
|
|
uint32_t UlvSettings;
|
||
|
|
uint32_t Reserved[37];
|
||
|
|
uint32_t Signature;
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU71_Firmware_Header SMU71_Firmware_Header;
|
||
|
|
|
||
|
|
struct SMU7_HystController_Data
|
||
|
|
{
|
||
|
|
uint8_t waterfall_up;
|
||
|
|
uint8_t waterfall_down;
|
||
|
|
uint8_t pstate;
|
||
|
|
uint8_t clamp_mode;
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU7_HystController_Data SMU7_HystController_Data;
|
||
|
|
|
||
|
|
#define SMU71_FIRMWARE_HEADER_LOCATION 0x20000
|
||
|
|
|
||
|
|
enum DisplayConfig {
|
||
|
|
PowerDown = 1,
|
||
|
|
DP54x4,
|
||
|
|
DP54x2,
|
||
|
|
DP54x1,
|
||
|
|
DP27x4,
|
||
|
|
DP27x2,
|
||
|
|
DP27x1,
|
||
|
|
HDMI297,
|
||
|
|
HDMI162,
|
||
|
|
LVDS,
|
||
|
|
DP324x4,
|
||
|
|
DP324x2,
|
||
|
|
DP324x1
|
||
|
|
};
|
||
|
|
|
||
|
|
//#define SX_BLOCK_COUNT 8
|
||
|
|
//#define MC_BLOCK_COUNT 1
|
||
|
|
//#define CPL_BLOCK_COUNT 27
|
||
|
|
|
||
|
|
#if defined SMU__VARIANT__ICELAND
|
||
|
|
#define SX_BLOCK_COUNT 8
|
||
|
|
#define MC_BLOCK_COUNT 1
|
||
|
|
#define CPL_BLOCK_COUNT 29
|
||
|
|
#endif
|
||
|
|
|
||
|
|
struct SMU7_Local_Cac {
|
||
|
|
uint8_t BlockId;
|
||
|
|
uint8_t SignalId;
|
||
|
|
uint8_t Threshold;
|
||
|
|
uint8_t Padding;
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU7_Local_Cac SMU7_Local_Cac;
|
||
|
|
|
||
|
|
struct SMU7_Local_Cac_Table {
|
||
|
|
SMU7_Local_Cac SxLocalCac[SX_BLOCK_COUNT];
|
||
|
|
SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
|
||
|
|
SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
|
||
|
|
|
||
|
|
#if !defined(SMC_MICROCODE)
|
||
|
|
#pragma pack(pop)
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif
|
||
|
|
|