309 lines
8.8 KiB
C
309 lines
8.8 KiB
C
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef _AMD_POWERPLAY_H_
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#define _AMD_POWERPLAY_H_
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#include <linux/seq_file.h>
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#include <linux/types.h>
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#include <linux/errno.h>
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#include "amd_shared.h"
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#include "cgs_common.h"
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#include "dm_pp_interface.h"
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extern const struct amd_ip_funcs pp_ip_funcs;
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extern const struct amd_pm_funcs pp_dpm_funcs;
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enum amd_pp_sensors {
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AMDGPU_PP_SENSOR_GFX_SCLK = 0,
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AMDGPU_PP_SENSOR_VDDNB,
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AMDGPU_PP_SENSOR_VDDGFX,
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AMDGPU_PP_SENSOR_UVD_VCLK,
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AMDGPU_PP_SENSOR_UVD_DCLK,
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AMDGPU_PP_SENSOR_VCE_ECCLK,
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AMDGPU_PP_SENSOR_GPU_LOAD,
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AMDGPU_PP_SENSOR_GFX_MCLK,
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AMDGPU_PP_SENSOR_GPU_TEMP,
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AMDGPU_PP_SENSOR_VCE_POWER,
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AMDGPU_PP_SENSOR_UVD_POWER,
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AMDGPU_PP_SENSOR_GPU_POWER,
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};
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enum amd_pp_task {
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AMD_PP_TASK_DISPLAY_CONFIG_CHANGE,
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AMD_PP_TASK_ENABLE_USER_STATE,
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AMD_PP_TASK_READJUST_POWER_STATE,
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AMD_PP_TASK_COMPLETE_INIT,
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AMD_PP_TASK_MAX
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};
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struct amd_pp_init {
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struct cgs_device *device;
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uint32_t chip_family;
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uint32_t chip_id;
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bool pm_en;
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uint32_t feature_mask;
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};
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enum amd_pp_display_config_type{
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AMD_PP_DisplayConfigType_None = 0,
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AMD_PP_DisplayConfigType_DP54 ,
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AMD_PP_DisplayConfigType_DP432 ,
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AMD_PP_DisplayConfigType_DP324 ,
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AMD_PP_DisplayConfigType_DP27,
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AMD_PP_DisplayConfigType_DP243,
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AMD_PP_DisplayConfigType_DP216,
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AMD_PP_DisplayConfigType_DP162,
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AMD_PP_DisplayConfigType_HDMI6G ,
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AMD_PP_DisplayConfigType_HDMI297 ,
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AMD_PP_DisplayConfigType_HDMI162,
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AMD_PP_DisplayConfigType_LVDS,
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AMD_PP_DisplayConfigType_DVI,
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AMD_PP_DisplayConfigType_WIRELESS,
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AMD_PP_DisplayConfigType_VGA
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};
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struct single_display_configuration
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{
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uint32_t controller_index;
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uint32_t controller_id;
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uint32_t signal_type;
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uint32_t display_state;
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/* phy id for the primary internal transmitter */
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uint8_t primary_transmitter_phyi_d;
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/* bitmap with the active lanes */
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uint8_t primary_transmitter_active_lanemap;
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/* phy id for the secondary internal transmitter (for dual-link dvi) */
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uint8_t secondary_transmitter_phy_id;
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/* bitmap with the active lanes */
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uint8_t secondary_transmitter_active_lanemap;
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/* misc phy settings for SMU. */
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uint32_t config_flags;
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uint32_t display_type;
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uint32_t view_resolution_cx;
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uint32_t view_resolution_cy;
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enum amd_pp_display_config_type displayconfigtype;
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uint32_t vertical_refresh; /* for active display */
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};
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#define MAX_NUM_DISPLAY 32
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struct amd_pp_display_configuration {
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bool nb_pstate_switch_disable;/* controls NB PState switch */
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bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
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bool cpu_pstate_disable;
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uint32_t cpu_pstate_separation_time;
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uint32_t num_display; /* total number of display*/
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uint32_t num_path_including_non_display;
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uint32_t crossfire_display_index;
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uint32_t min_mem_set_clock;
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uint32_t min_core_set_clock;
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/* unit 10KHz x bit*/
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uint32_t min_bus_bandwidth;
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/* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
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uint32_t min_core_set_clock_in_sr;
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struct single_display_configuration displays[MAX_NUM_DISPLAY];
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uint32_t vrefresh; /* for active display*/
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uint32_t min_vblank_time; /* for active display*/
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bool multi_monitor_in_sync;
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/* Controller Index of primary display - used in MCLK SMC switching hang
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* SW Workaround*/
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uint32_t crtc_index;
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/* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
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uint32_t line_time_in_us;
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bool invalid_vblank_time;
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uint32_t display_clk;
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/*
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* for given display configuration if multimonitormnsync == false then
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* Memory clock DPMS with this latency or below is allowed, DPMS with
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* higher latency not allowed.
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*/
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uint32_t dce_tolerable_mclk_in_active_latency;
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uint32_t min_dcef_set_clk;
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uint32_t min_dcef_deep_sleep_set_clk;
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};
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struct amd_pp_simple_clock_info {
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uint32_t engine_max_clock;
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uint32_t memory_max_clock;
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uint32_t level;
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};
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enum PP_DAL_POWERLEVEL {
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PP_DAL_POWERLEVEL_INVALID = 0,
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PP_DAL_POWERLEVEL_ULTRALOW,
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PP_DAL_POWERLEVEL_LOW,
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PP_DAL_POWERLEVEL_NOMINAL,
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PP_DAL_POWERLEVEL_PERFORMANCE,
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PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
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PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
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PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
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PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
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PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
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PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
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PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
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PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
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};
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struct amd_pp_clock_info {
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uint32_t min_engine_clock;
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uint32_t max_engine_clock;
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uint32_t min_memory_clock;
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uint32_t max_memory_clock;
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uint32_t min_bus_bandwidth;
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uint32_t max_bus_bandwidth;
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uint32_t max_engine_clock_in_sr;
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uint32_t min_engine_clock_in_sr;
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enum PP_DAL_POWERLEVEL max_clocks_state;
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};
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enum amd_pp_clock_type {
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amd_pp_disp_clock = 1,
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amd_pp_sys_clock,
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amd_pp_mem_clock,
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amd_pp_dcef_clock,
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amd_pp_soc_clock,
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amd_pp_pixel_clock,
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amd_pp_phy_clock,
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amd_pp_dcf_clock,
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amd_pp_dpp_clock,
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amd_pp_f_clock = amd_pp_dcef_clock,
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};
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#define MAX_NUM_CLOCKS 16
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struct amd_pp_clocks {
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uint32_t count;
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uint32_t clock[MAX_NUM_CLOCKS];
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uint32_t latency[MAX_NUM_CLOCKS];
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};
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enum {
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PP_GROUP_UNKNOWN = 0,
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PP_GROUP_GFX = 1,
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PP_GROUP_SYS,
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PP_GROUP_MAX
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};
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struct pp_states_info {
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uint32_t nums;
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uint32_t states[16];
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};
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struct pp_gpu_power {
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uint32_t vddc_power;
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uint32_t vddci_power;
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uint32_t max_gpu_power;
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uint32_t average_gpu_power;
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};
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struct pp_display_clock_request {
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enum amd_pp_clock_type clock_type;
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uint32_t clock_freq_in_khz;
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};
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#define PP_GROUP_MASK 0xF0000000
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#define PP_GROUP_SHIFT 28
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#define PP_BLOCK_MASK 0x0FFFFF00
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#define PP_BLOCK_SHIFT 8
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#define PP_BLOCK_GFX_CG 0x01
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#define PP_BLOCK_GFX_MG 0x02
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#define PP_BLOCK_GFX_3D 0x04
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#define PP_BLOCK_GFX_RLC 0x08
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#define PP_BLOCK_GFX_CP 0x10
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#define PP_BLOCK_SYS_BIF 0x01
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#define PP_BLOCK_SYS_MC 0x02
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#define PP_BLOCK_SYS_ROM 0x04
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#define PP_BLOCK_SYS_DRM 0x08
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#define PP_BLOCK_SYS_HDP 0x10
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#define PP_BLOCK_SYS_SDMA 0x20
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#define PP_STATE_MASK 0x0000000F
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#define PP_STATE_SHIFT 0
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#define PP_STATE_SUPPORT_MASK 0x000000F0
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#define PP_STATE_SUPPORT_SHIFT 0
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#define PP_STATE_CG 0x01
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#define PP_STATE_LS 0x02
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#define PP_STATE_DS 0x04
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#define PP_STATE_SD 0x08
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#define PP_STATE_SUPPORT_CG 0x10
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#define PP_STATE_SUPPORT_LS 0x20
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#define PP_STATE_SUPPORT_DS 0x40
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#define PP_STATE_SUPPORT_SD 0x80
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#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
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block << PP_BLOCK_SHIFT |\
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support << PP_STATE_SUPPORT_SHIFT |\
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state << PP_STATE_SHIFT)
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struct amd_powerplay {
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struct cgs_device *cgs_device;
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void *pp_handle;
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const struct amd_ip_funcs *ip_funcs;
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const struct amd_pm_funcs *pp_funcs;
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};
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int amd_powerplay_reset(void *handle);
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int amd_powerplay_display_configuration_change(void *handle,
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const struct amd_pp_display_configuration *input);
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int amd_powerplay_get_display_power_level(void *handle,
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struct amd_pp_simple_clock_info *output);
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int amd_powerplay_get_current_clocks(void *handle,
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struct amd_pp_clock_info *output);
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int amd_powerplay_get_clock_by_type(void *handle,
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enum amd_pp_clock_type type,
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struct amd_pp_clocks *clocks);
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int amd_powerplay_get_clock_by_type_with_latency(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_latency *clocks);
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int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks);
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int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
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int amd_powerplay_display_clock_voltage_request(void *handle,
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struct pp_display_clock_request *clock);
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int amd_powerplay_get_display_mode_validation_clocks(void *handle,
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struct amd_pp_simple_clock_info *output);
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#endif /* _AMD_POWERPLAY_H_ */
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