439 lines
12 KiB
C
439 lines
12 KiB
C
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/*
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* Copyright 2011 Red Hat Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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*/
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/*
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* Authors:
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* Jerome Glisse <glisse@freedesktop.org>
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*/
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/* Algorithm:
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*
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* We store the last allocated bo in "hole", we always try to allocate
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* after the last allocated bo. Principle is that in a linear GPU ring
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* progression was is after last is the oldest bo we allocated and thus
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* the first one that should no longer be in use by the GPU.
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*
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* If it's not the case we skip over the bo after last to the closest
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* done bo if such one exist. If none exist and we are not asked to
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* block we report failure to allocate.
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*
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* If we are asked to block we wait on all the oldest fence of all
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* rings. We just wait for any of those fence to complete.
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*/
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#include <drm/drmP.h>
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#include "amdgpu.h"
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static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo);
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static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager,
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unsigned size, u32 align, u32 domain)
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{
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int i, r;
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init_waitqueue_head(&sa_manager->wq);
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sa_manager->bo = NULL;
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sa_manager->size = size;
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sa_manager->domain = domain;
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sa_manager->align = align;
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sa_manager->hole = &sa_manager->olist;
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INIT_LIST_HEAD(&sa_manager->olist);
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for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
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INIT_LIST_HEAD(&sa_manager->flist[i]);
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r = amdgpu_bo_create(adev, size, align, true, domain,
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0, NULL, NULL, 0, &sa_manager->bo);
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if (r) {
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dev_err(adev->dev, "(%d) failed to allocate bo for manager\n", r);
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return r;
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}
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return r;
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}
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void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager)
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{
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struct amdgpu_sa_bo *sa_bo, *tmp;
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if (!list_empty(&sa_manager->olist)) {
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sa_manager->hole = &sa_manager->olist,
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amdgpu_sa_bo_try_free(sa_manager);
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if (!list_empty(&sa_manager->olist)) {
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dev_err(adev->dev, "sa_manager is not empty, clearing anyway\n");
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}
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}
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list_for_each_entry_safe(sa_bo, tmp, &sa_manager->olist, olist) {
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amdgpu_sa_bo_remove_locked(sa_bo);
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}
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amdgpu_bo_unref(&sa_manager->bo);
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sa_manager->size = 0;
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}
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int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager)
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{
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int r;
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if (sa_manager->bo == NULL) {
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dev_err(adev->dev, "no bo for sa manager\n");
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return -EINVAL;
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}
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/* map the buffer */
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r = amdgpu_bo_reserve(sa_manager->bo, false);
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if (r) {
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dev_err(adev->dev, "(%d) failed to reserve manager bo\n", r);
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return r;
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}
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r = amdgpu_bo_pin(sa_manager->bo, sa_manager->domain, &sa_manager->gpu_addr);
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if (r) {
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amdgpu_bo_unreserve(sa_manager->bo);
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dev_err(adev->dev, "(%d) failed to pin manager bo\n", r);
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return r;
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}
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r = amdgpu_bo_kmap(sa_manager->bo, &sa_manager->cpu_ptr);
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memset(sa_manager->cpu_ptr, 0, sa_manager->size);
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amdgpu_bo_unreserve(sa_manager->bo);
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return r;
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}
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int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager)
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{
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int r;
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if (sa_manager->bo == NULL) {
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dev_err(adev->dev, "no bo for sa manager\n");
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return -EINVAL;
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}
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r = amdgpu_bo_reserve(sa_manager->bo, true);
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if (!r) {
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amdgpu_bo_kunmap(sa_manager->bo);
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amdgpu_bo_unpin(sa_manager->bo);
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amdgpu_bo_unreserve(sa_manager->bo);
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}
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return r;
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}
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static void amdgpu_sa_bo_remove_locked(struct amdgpu_sa_bo *sa_bo)
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{
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struct amdgpu_sa_manager *sa_manager = sa_bo->manager;
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if (sa_manager->hole == &sa_bo->olist) {
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sa_manager->hole = sa_bo->olist.prev;
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}
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list_del_init(&sa_bo->olist);
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list_del_init(&sa_bo->flist);
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dma_fence_put(sa_bo->fence);
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kfree(sa_bo);
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}
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static void amdgpu_sa_bo_try_free(struct amdgpu_sa_manager *sa_manager)
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{
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struct amdgpu_sa_bo *sa_bo, *tmp;
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if (sa_manager->hole->next == &sa_manager->olist)
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return;
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sa_bo = list_entry(sa_manager->hole->next, struct amdgpu_sa_bo, olist);
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list_for_each_entry_safe_from(sa_bo, tmp, &sa_manager->olist, olist) {
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if (sa_bo->fence == NULL ||
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!dma_fence_is_signaled(sa_bo->fence)) {
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return;
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}
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amdgpu_sa_bo_remove_locked(sa_bo);
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}
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}
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static inline unsigned amdgpu_sa_bo_hole_soffset(struct amdgpu_sa_manager *sa_manager)
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{
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struct list_head *hole = sa_manager->hole;
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if (hole != &sa_manager->olist) {
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return list_entry(hole, struct amdgpu_sa_bo, olist)->eoffset;
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}
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return 0;
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}
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static inline unsigned amdgpu_sa_bo_hole_eoffset(struct amdgpu_sa_manager *sa_manager)
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{
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struct list_head *hole = sa_manager->hole;
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if (hole->next != &sa_manager->olist) {
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return list_entry(hole->next, struct amdgpu_sa_bo, olist)->soffset;
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}
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return sa_manager->size;
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}
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static bool amdgpu_sa_bo_try_alloc(struct amdgpu_sa_manager *sa_manager,
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struct amdgpu_sa_bo *sa_bo,
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unsigned size, unsigned align)
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{
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unsigned soffset, eoffset, wasted;
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soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
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eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
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wasted = (align - (soffset % align)) % align;
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if ((eoffset - soffset) >= (size + wasted)) {
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soffset += wasted;
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sa_bo->manager = sa_manager;
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sa_bo->soffset = soffset;
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sa_bo->eoffset = soffset + size;
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list_add(&sa_bo->olist, sa_manager->hole);
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INIT_LIST_HEAD(&sa_bo->flist);
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sa_manager->hole = &sa_bo->olist;
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return true;
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}
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return false;
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}
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/**
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* amdgpu_sa_event - Check if we can stop waiting
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*
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* @sa_manager: pointer to the sa_manager
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* @size: number of bytes we want to allocate
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* @align: alignment we need to match
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*
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* Check if either there is a fence we can wait for or
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* enough free memory to satisfy the allocation directly
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*/
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static bool amdgpu_sa_event(struct amdgpu_sa_manager *sa_manager,
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unsigned size, unsigned align)
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{
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unsigned soffset, eoffset, wasted;
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int i;
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for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
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if (!list_empty(&sa_manager->flist[i]))
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return true;
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soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
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eoffset = amdgpu_sa_bo_hole_eoffset(sa_manager);
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wasted = (align - (soffset % align)) % align;
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if ((eoffset - soffset) >= (size + wasted)) {
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return true;
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}
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return false;
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}
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static bool amdgpu_sa_bo_next_hole(struct amdgpu_sa_manager *sa_manager,
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struct dma_fence **fences,
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unsigned *tries)
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{
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struct amdgpu_sa_bo *best_bo = NULL;
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unsigned i, soffset, best, tmp;
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/* if hole points to the end of the buffer */
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if (sa_manager->hole->next == &sa_manager->olist) {
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/* try again with its beginning */
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sa_manager->hole = &sa_manager->olist;
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return true;
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}
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soffset = amdgpu_sa_bo_hole_soffset(sa_manager);
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/* to handle wrap around we add sa_manager->size */
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best = sa_manager->size * 2;
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/* go over all fence list and try to find the closest sa_bo
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* of the current last
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*/
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for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i) {
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struct amdgpu_sa_bo *sa_bo;
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if (list_empty(&sa_manager->flist[i]))
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continue;
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sa_bo = list_first_entry(&sa_manager->flist[i],
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struct amdgpu_sa_bo, flist);
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if (!dma_fence_is_signaled(sa_bo->fence)) {
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fences[i] = sa_bo->fence;
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continue;
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}
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/* limit the number of tries each ring gets */
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if (tries[i] > 2) {
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continue;
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}
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tmp = sa_bo->soffset;
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if (tmp < soffset) {
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/* wrap around, pretend it's after */
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tmp += sa_manager->size;
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}
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tmp -= soffset;
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if (tmp < best) {
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/* this sa bo is the closest one */
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best = tmp;
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best_bo = sa_bo;
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}
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}
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if (best_bo) {
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uint32_t idx = best_bo->fence->context;
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idx %= AMDGPU_SA_NUM_FENCE_LISTS;
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++tries[idx];
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sa_manager->hole = best_bo->olist.prev;
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/* we knew that this one is signaled,
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so it's save to remote it */
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amdgpu_sa_bo_remove_locked(best_bo);
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return true;
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}
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return false;
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}
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int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
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struct amdgpu_sa_bo **sa_bo,
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unsigned size, unsigned align)
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{
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struct dma_fence *fences[AMDGPU_SA_NUM_FENCE_LISTS];
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unsigned tries[AMDGPU_SA_NUM_FENCE_LISTS];
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unsigned count;
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int i, r;
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signed long t;
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if (WARN_ON_ONCE(align > sa_manager->align))
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return -EINVAL;
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if (WARN_ON_ONCE(size > sa_manager->size))
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return -EINVAL;
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*sa_bo = kmalloc(sizeof(struct amdgpu_sa_bo), GFP_KERNEL);
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if (!(*sa_bo))
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return -ENOMEM;
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(*sa_bo)->manager = sa_manager;
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(*sa_bo)->fence = NULL;
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INIT_LIST_HEAD(&(*sa_bo)->olist);
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INIT_LIST_HEAD(&(*sa_bo)->flist);
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spin_lock(&sa_manager->wq.lock);
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do {
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for (i = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i) {
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fences[i] = NULL;
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tries[i] = 0;
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}
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do {
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amdgpu_sa_bo_try_free(sa_manager);
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if (amdgpu_sa_bo_try_alloc(sa_manager, *sa_bo,
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size, align)) {
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spin_unlock(&sa_manager->wq.lock);
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return 0;
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}
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/* see if we can skip over some allocations */
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} while (amdgpu_sa_bo_next_hole(sa_manager, fences, tries));
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for (i = 0, count = 0; i < AMDGPU_SA_NUM_FENCE_LISTS; ++i)
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if (fences[i])
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fences[count++] = dma_fence_get(fences[i]);
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if (count) {
|
||
|
|
spin_unlock(&sa_manager->wq.lock);
|
||
|
|
t = dma_fence_wait_any_timeout(fences, count, false,
|
||
|
|
MAX_SCHEDULE_TIMEOUT,
|
||
|
|
NULL);
|
||
|
|
for (i = 0; i < count; ++i)
|
||
|
|
dma_fence_put(fences[i]);
|
||
|
|
|
||
|
|
r = (t > 0) ? 0 : t;
|
||
|
|
spin_lock(&sa_manager->wq.lock);
|
||
|
|
} else {
|
||
|
|
/* if we have nothing to wait for block */
|
||
|
|
r = wait_event_interruptible_locked(
|
||
|
|
sa_manager->wq,
|
||
|
|
amdgpu_sa_event(sa_manager, size, align)
|
||
|
|
);
|
||
|
|
}
|
||
|
|
|
||
|
|
} while (!r);
|
||
|
|
|
||
|
|
spin_unlock(&sa_manager->wq.lock);
|
||
|
|
kfree(*sa_bo);
|
||
|
|
*sa_bo = NULL;
|
||
|
|
return r;
|
||
|
|
}
|
||
|
|
|
||
|
|
void amdgpu_sa_bo_free(struct amdgpu_device *adev, struct amdgpu_sa_bo **sa_bo,
|
||
|
|
struct dma_fence *fence)
|
||
|
|
{
|
||
|
|
struct amdgpu_sa_manager *sa_manager;
|
||
|
|
|
||
|
|
if (sa_bo == NULL || *sa_bo == NULL) {
|
||
|
|
return;
|
||
|
|
}
|
||
|
|
|
||
|
|
sa_manager = (*sa_bo)->manager;
|
||
|
|
spin_lock(&sa_manager->wq.lock);
|
||
|
|
if (fence && !dma_fence_is_signaled(fence)) {
|
||
|
|
uint32_t idx;
|
||
|
|
|
||
|
|
(*sa_bo)->fence = dma_fence_get(fence);
|
||
|
|
idx = fence->context % AMDGPU_SA_NUM_FENCE_LISTS;
|
||
|
|
list_add_tail(&(*sa_bo)->flist, &sa_manager->flist[idx]);
|
||
|
|
} else {
|
||
|
|
amdgpu_sa_bo_remove_locked(*sa_bo);
|
||
|
|
}
|
||
|
|
wake_up_all_locked(&sa_manager->wq);
|
||
|
|
spin_unlock(&sa_manager->wq.lock);
|
||
|
|
*sa_bo = NULL;
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined(CONFIG_DEBUG_FS)
|
||
|
|
|
||
|
|
void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
|
||
|
|
struct seq_file *m)
|
||
|
|
{
|
||
|
|
struct amdgpu_sa_bo *i;
|
||
|
|
|
||
|
|
spin_lock(&sa_manager->wq.lock);
|
||
|
|
list_for_each_entry(i, &sa_manager->olist, olist) {
|
||
|
|
uint64_t soffset = i->soffset + sa_manager->gpu_addr;
|
||
|
|
uint64_t eoffset = i->eoffset + sa_manager->gpu_addr;
|
||
|
|
if (&i->olist == sa_manager->hole) {
|
||
|
|
seq_printf(m, ">");
|
||
|
|
} else {
|
||
|
|
seq_printf(m, " ");
|
||
|
|
}
|
||
|
|
seq_printf(m, "[0x%010llx 0x%010llx] size %8lld",
|
||
|
|
soffset, eoffset, eoffset - soffset);
|
||
|
|
|
||
|
|
if (i->fence)
|
||
|
|
seq_printf(m, " protected by 0x%08x on context %llu",
|
||
|
|
i->fence->seqno, i->fence->context);
|
||
|
|
|
||
|
|
seq_printf(m, "\n");
|
||
|
|
}
|
||
|
|
spin_unlock(&sa_manager->wq.lock);
|
||
|
|
}
|
||
|
|
#endif
|