155 lines
5.3 KiB
C
155 lines
5.3 KiB
C
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Author: Huang Rui
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*
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*/
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#ifndef __AMDGPU_PSP_H__
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#define __AMDGPU_PSP_H__
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#include "amdgpu.h"
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#include "psp_gfx_if.h"
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#define PSP_FENCE_BUFFER_SIZE 0x1000
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#define PSP_CMD_BUFFER_SIZE 0x1000
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#define PSP_ASD_SHARED_MEM_SIZE 0x4000
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#define PSP_1_MEG 0x100000
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enum psp_ring_type
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{
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PSP_RING_TYPE__INVALID = 0,
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/*
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* These values map to the way the PSP kernel identifies the
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* rings.
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*/
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PSP_RING_TYPE__UM = 1, /* User mode ring (formerly called RBI) */
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PSP_RING_TYPE__KM = 2 /* Kernel mode ring (formerly called GPCOM) */
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};
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struct psp_ring
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{
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enum psp_ring_type ring_type;
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struct psp_gfx_rb_frame *ring_mem;
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uint64_t ring_mem_mc_addr;
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void *ring_mem_handle;
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uint32_t ring_size;
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};
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struct psp_context
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{
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struct amdgpu_device *adev;
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struct psp_ring km_ring;
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struct psp_gfx_cmd_resp *cmd;
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int (*init_microcode)(struct psp_context *psp);
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int (*bootloader_load_sysdrv)(struct psp_context *psp);
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int (*bootloader_load_sos)(struct psp_context *psp);
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int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode,
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struct psp_gfx_cmd_resp *cmd);
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int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type);
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int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type);
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int (*ring_stop)(struct psp_context *psp,
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enum psp_ring_type ring_type);
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int (*ring_destroy)(struct psp_context *psp,
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enum psp_ring_type ring_type);
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int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode,
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uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index);
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bool (*compare_sram_data)(struct psp_context *psp,
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struct amdgpu_firmware_info *ucode,
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enum AMDGPU_UCODE_ID ucode_type);
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bool (*smu_reload_quirk)(struct psp_context *psp);
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int (*mode1_reset)(struct psp_context *psp);
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/* fence buffer */
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struct amdgpu_bo *fw_pri_bo;
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uint64_t fw_pri_mc_addr;
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void *fw_pri_buf;
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/* sos firmware */
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const struct firmware *sos_fw;
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uint32_t sos_fw_version;
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uint32_t sos_feature_version;
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uint32_t sys_bin_size;
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uint32_t sos_bin_size;
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uint8_t *sys_start_addr;
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uint8_t *sos_start_addr;
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/* tmr buffer */
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struct amdgpu_bo *tmr_bo;
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uint64_t tmr_mc_addr;
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void *tmr_buf;
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/* asd firmware and buffer */
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const struct firmware *asd_fw;
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uint32_t asd_fw_version;
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uint32_t asd_feature_version;
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uint32_t asd_ucode_size;
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uint8_t *asd_start_addr;
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struct amdgpu_bo *asd_shared_bo;
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uint64_t asd_shared_mc_addr;
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void *asd_shared_buf;
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/* fence buffer */
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struct amdgpu_bo *fence_buf_bo;
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uint64_t fence_buf_mc_addr;
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void *fence_buf;
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/* cmd buffer */
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struct amdgpu_bo *cmd_buf_bo;
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uint64_t cmd_buf_mc_addr;
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struct psp_gfx_cmd_resp *cmd_buf_mem;
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};
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struct amdgpu_psp_funcs {
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bool (*check_fw_loading_status)(struct amdgpu_device *adev,
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enum AMDGPU_UCODE_ID);
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};
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#define psp_prep_cmd_buf(ucode, type) (psp)->prep_cmd_buf((ucode), (type))
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#define psp_ring_init(psp, type) (psp)->ring_init((psp), (type))
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#define psp_ring_create(psp, type) (psp)->ring_create((psp), (type))
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#define psp_ring_stop(psp, type) (psp)->ring_stop((psp), (type))
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#define psp_ring_destroy(psp, type) ((psp)->ring_destroy((psp), (type)))
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#define psp_cmd_submit(psp, ucode, cmd_mc, fence_mc, index) \
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(psp)->cmd_submit((psp), (ucode), (cmd_mc), (fence_mc), (index))
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#define psp_compare_sram_data(psp, ucode, type) \
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(psp)->compare_sram_data((psp), (ucode), (type))
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#define psp_init_microcode(psp) \
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((psp)->init_microcode ? (psp)->init_microcode((psp)) : 0)
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#define psp_bootloader_load_sysdrv(psp) \
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((psp)->bootloader_load_sysdrv ? (psp)->bootloader_load_sysdrv((psp)) : 0)
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#define psp_bootloader_load_sos(psp) \
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((psp)->bootloader_load_sos ? (psp)->bootloader_load_sos((psp)) : 0)
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#define psp_smu_reload_quirk(psp) \
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((psp)->smu_reload_quirk ? (psp)->smu_reload_quirk((psp)) : false)
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#define psp_mode1_reset(psp) \
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((psp)->mode1_reset ? (psp)->mode1_reset((psp)) : false)
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extern const struct amd_ip_funcs psp_ip_funcs;
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extern const struct amdgpu_ip_block_version psp_v3_1_ip_block;
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extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
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uint32_t field_val, uint32_t mask, bool check_changed);
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extern const struct amdgpu_ip_block_version psp_v10_0_ip_block;
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#endif
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