291 lines
7.3 KiB
C
291 lines
7.3 KiB
C
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include "atom.h"
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#include "amdgpu.h"
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#include "amd_shared.h"
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include "amdgpu_pm.h"
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#include <drm/amdgpu_drm.h>
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#include "amdgpu_powerplay.h"
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#include "si_dpm.h"
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#include "cik_dpm.h"
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#include "vi_dpm.h"
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static int amdgpu_pp_early_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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struct amd_powerplay *amd_pp;
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int ret = 0;
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amd_pp = &(adev->powerplay);
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amd_pp->pp_handle = (void *)adev;
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switch (adev->asic_type) {
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case CHIP_POLARIS11:
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case CHIP_POLARIS10:
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case CHIP_POLARIS12:
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case CHIP_TONGA:
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case CHIP_FIJI:
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case CHIP_TOPAZ:
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case CHIP_CARRIZO:
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case CHIP_STONEY:
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case CHIP_VEGA10:
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case CHIP_RAVEN:
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amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
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amd_pp->ip_funcs = &pp_ip_funcs;
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amd_pp->pp_funcs = &pp_dpm_funcs;
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break;
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/* These chips don't have powerplay implemenations */
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#ifdef CONFIG_DRM_AMDGPU_SI
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case CHIP_TAHITI:
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case CHIP_PITCAIRN:
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case CHIP_VERDE:
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case CHIP_OLAND:
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case CHIP_HAINAN:
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amd_pp->ip_funcs = &si_dpm_ip_funcs;
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amd_pp->pp_funcs = &si_dpm_funcs;
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break;
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#endif
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#ifdef CONFIG_DRM_AMDGPU_CIK
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case CHIP_BONAIRE:
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case CHIP_HAWAII:
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if (amdgpu_dpm == -1) {
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amd_pp->ip_funcs = &ci_dpm_ip_funcs;
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amd_pp->pp_funcs = &ci_dpm_funcs;
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} else {
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amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
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amd_pp->ip_funcs = &pp_ip_funcs;
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amd_pp->pp_funcs = &pp_dpm_funcs;
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}
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break;
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case CHIP_KABINI:
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case CHIP_MULLINS:
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case CHIP_KAVERI:
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amd_pp->ip_funcs = &kv_dpm_ip_funcs;
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amd_pp->pp_funcs = &kv_dpm_funcs;
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break;
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#endif
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default:
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ret = -EINVAL;
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break;
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}
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if (adev->powerplay.ip_funcs->early_init)
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ret = adev->powerplay.ip_funcs->early_init(
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amd_pp->cgs_device ? amd_pp->cgs_device :
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amd_pp->pp_handle);
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return ret;
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}
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static int amdgpu_pp_late_init(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->late_init)
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ret = adev->powerplay.ip_funcs->late_init(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_sw_init(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->sw_init)
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ret = adev->powerplay.ip_funcs->sw_init(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_sw_fini(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->sw_fini)
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ret = adev->powerplay.ip_funcs->sw_fini(
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adev->powerplay.pp_handle);
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if (ret)
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return ret;
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return ret;
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}
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static int amdgpu_pp_hw_init(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
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amdgpu_ucode_init_bo(adev);
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if (adev->powerplay.ip_funcs->hw_init)
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ret = adev->powerplay.ip_funcs->hw_init(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_hw_fini(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->hw_fini)
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ret = adev->powerplay.ip_funcs->hw_fini(
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adev->powerplay.pp_handle);
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if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
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amdgpu_ucode_fini_bo(adev);
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return ret;
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}
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static void amdgpu_pp_late_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->late_fini)
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adev->powerplay.ip_funcs->late_fini(
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adev->powerplay.pp_handle);
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if (adev->powerplay.cgs_device)
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amdgpu_cgs_destroy_device(adev->powerplay.cgs_device);
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}
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static int amdgpu_pp_suspend(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->suspend)
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ret = adev->powerplay.ip_funcs->suspend(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_resume(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->resume)
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ret = adev->powerplay.ip_funcs->resume(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_set_clockgating_state(void *handle,
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enum amd_clockgating_state state)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->set_clockgating_state)
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ret = adev->powerplay.ip_funcs->set_clockgating_state(
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adev->powerplay.pp_handle, state);
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return ret;
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}
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static int amdgpu_pp_set_powergating_state(void *handle,
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enum amd_powergating_state state)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->set_powergating_state)
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ret = adev->powerplay.ip_funcs->set_powergating_state(
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adev->powerplay.pp_handle, state);
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return ret;
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}
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static bool amdgpu_pp_is_idle(void *handle)
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{
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bool ret = true;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->is_idle)
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ret = adev->powerplay.ip_funcs->is_idle(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_wait_for_idle(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->wait_for_idle)
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ret = adev->powerplay.ip_funcs->wait_for_idle(
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adev->powerplay.pp_handle);
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return ret;
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}
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static int amdgpu_pp_soft_reset(void *handle)
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{
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int ret = 0;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->powerplay.ip_funcs->soft_reset)
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ret = adev->powerplay.ip_funcs->soft_reset(
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adev->powerplay.pp_handle);
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return ret;
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}
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static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
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.name = "amdgpu_powerplay",
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.early_init = amdgpu_pp_early_init,
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.late_init = amdgpu_pp_late_init,
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.sw_init = amdgpu_pp_sw_init,
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.sw_fini = amdgpu_pp_sw_fini,
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.hw_init = amdgpu_pp_hw_init,
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.hw_fini = amdgpu_pp_hw_fini,
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.late_fini = amdgpu_pp_late_fini,
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.suspend = amdgpu_pp_suspend,
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.resume = amdgpu_pp_resume,
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.is_idle = amdgpu_pp_is_idle,
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.wait_for_idle = amdgpu_pp_wait_for_idle,
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.soft_reset = amdgpu_pp_soft_reset,
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.set_clockgating_state = amdgpu_pp_set_clockgating_state,
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.set_powergating_state = amdgpu_pp_set_powergating_state,
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};
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const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
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{
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.type = AMD_IP_BLOCK_TYPE_SMC,
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.major = 1,
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.minor = 0,
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.rev = 0,
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.funcs = &amdgpu_pp_ip_funcs,
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};
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