300 lines
9.1 KiB
C
300 lines
9.1 KiB
C
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/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#ifndef __AMDGPU_OBJECT_H__
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#define __AMDGPU_OBJECT_H__
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#include <drm/amdgpu_drm.h>
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#include "amdgpu.h"
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#define AMDGPU_BO_INVALID_OFFSET LONG_MAX
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/* bo virtual addresses in a vm */
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struct amdgpu_bo_va_mapping {
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struct amdgpu_bo_va *bo_va;
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struct list_head list;
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struct rb_node rb;
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uint64_t start;
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uint64_t last;
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uint64_t __subtree_last;
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uint64_t offset;
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uint64_t flags;
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};
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/* User space allocated BO in a VM */
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struct amdgpu_bo_va {
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struct amdgpu_vm_bo_base base;
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/* protected by bo being reserved */
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unsigned ref_count;
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/* all other members protected by the VM PD being reserved */
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struct dma_fence *last_pt_update;
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/* mappings for this bo_va */
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struct list_head invalids;
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struct list_head valids;
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/* If the mappings are cleared or filled */
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bool cleared;
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};
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struct amdgpu_bo {
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/* Protected by tbo.reserved */
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u32 preferred_domains;
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u32 allowed_domains;
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struct ttm_place placements[AMDGPU_GEM_DOMAIN_MAX + 1];
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struct ttm_placement placement;
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struct ttm_buffer_object tbo;
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struct ttm_bo_kmap_obj kmap;
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u64 flags;
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unsigned pin_count;
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u64 tiling_flags;
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u64 metadata_flags;
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void *metadata;
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u32 metadata_size;
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unsigned prime_shared_count;
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/* list of all virtual address to which this bo is associated to */
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struct list_head va;
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/* Constant after initialization */
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struct drm_gem_object gem_base;
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struct amdgpu_bo *parent;
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struct amdgpu_bo *shadow;
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struct ttm_bo_kmap_obj dma_buf_vmap;
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struct amdgpu_mn *mn;
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union {
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struct list_head mn_list;
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struct list_head shadow_list;
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};
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};
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static inline struct amdgpu_bo *ttm_to_amdgpu_bo(struct ttm_buffer_object *tbo)
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{
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return container_of(tbo, struct amdgpu_bo, tbo);
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}
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/**
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* amdgpu_mem_type_to_domain - return domain corresponding to mem_type
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* @mem_type: ttm memory type
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*
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* Returns corresponding domain of the ttm mem_type
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*/
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static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
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{
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switch (mem_type) {
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case TTM_PL_VRAM:
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return AMDGPU_GEM_DOMAIN_VRAM;
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case TTM_PL_TT:
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return AMDGPU_GEM_DOMAIN_GTT;
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case TTM_PL_SYSTEM:
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return AMDGPU_GEM_DOMAIN_CPU;
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case AMDGPU_PL_GDS:
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return AMDGPU_GEM_DOMAIN_GDS;
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case AMDGPU_PL_GWS:
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return AMDGPU_GEM_DOMAIN_GWS;
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case AMDGPU_PL_OA:
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return AMDGPU_GEM_DOMAIN_OA;
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default:
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break;
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}
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return 0;
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}
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/**
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* amdgpu_bo_reserve - reserve bo
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* @bo: bo structure
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* @no_intr: don't return -ERESTARTSYS on pending signal
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*
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* Returns:
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* -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
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* a signal. Release all buffer reservations and return to user-space.
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*/
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static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
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{
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struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
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int r;
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r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL);
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if (unlikely(r != 0)) {
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if (r != -ERESTARTSYS)
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dev_err(adev->dev, "%p reserve failed\n", bo);
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return r;
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}
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return 0;
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}
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static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
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{
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ttm_bo_unreserve(&bo->tbo);
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}
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static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
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{
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return bo->tbo.num_pages << PAGE_SHIFT;
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}
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static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
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{
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return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
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}
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static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
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{
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return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
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}
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/**
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* amdgpu_bo_mmap_offset - return mmap offset of bo
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* @bo: amdgpu object for which we query the offset
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*
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* Returns mmap offset of the object.
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*/
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static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
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{
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return drm_vma_node_offset_addr(&bo->tbo.vma_node);
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}
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/**
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* amdgpu_bo_gpu_accessible - return whether the bo is currently in memory that
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* is accessible to the GPU.
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*/
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static inline bool amdgpu_bo_gpu_accessible(struct amdgpu_bo *bo)
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{
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switch (bo->tbo.mem.mem_type) {
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case TTM_PL_TT: return amdgpu_ttm_is_bound(bo->tbo.ttm);
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case TTM_PL_VRAM: return true;
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default: return false;
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}
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}
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/**
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* amdgpu_bo_explicit_sync - return whether the bo is explicitly synced
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*/
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static inline bool amdgpu_bo_explicit_sync(struct amdgpu_bo *bo)
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{
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return bo->flags & AMDGPU_GEM_CREATE_EXPLICIT_SYNC;
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}
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int amdgpu_bo_create(struct amdgpu_device *adev,
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unsigned long size, int byte_align,
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bool kernel, u32 domain, u64 flags,
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struct sg_table *sg,
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struct reservation_object *resv,
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uint64_t init_value,
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struct amdgpu_bo **bo_ptr);
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int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
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unsigned long size, int align,
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u32 domain, struct amdgpu_bo **bo_ptr,
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u64 *gpu_addr, void **cpu_addr);
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int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
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unsigned long size, int align,
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u32 domain, struct amdgpu_bo **bo_ptr,
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u64 *gpu_addr, void **cpu_addr);
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void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
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void **cpu_addr);
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int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
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void *amdgpu_bo_kptr(struct amdgpu_bo *bo);
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void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
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struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
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void amdgpu_bo_unref(struct amdgpu_bo **bo);
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int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
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int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
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u64 min_offset, u64 max_offset,
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u64 *gpu_addr);
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int amdgpu_bo_unpin(struct amdgpu_bo *bo);
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int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
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int amdgpu_bo_init(struct amdgpu_device *adev);
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void amdgpu_bo_fini(struct amdgpu_device *adev);
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int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
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struct vm_area_struct *vma);
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int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
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void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
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int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
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uint32_t metadata_size, uint64_t flags);
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int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
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size_t buffer_size, uint32_t *metadata_size,
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uint64_t *flags);
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void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
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bool evict,
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struct ttm_mem_reg *new_mem);
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int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
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void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
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bool shared);
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u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo);
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int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
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struct amdgpu_ring *ring,
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struct amdgpu_bo *bo,
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struct reservation_object *resv,
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struct dma_fence **fence, bool direct);
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int amdgpu_bo_validate(struct amdgpu_bo *bo);
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int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
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struct amdgpu_ring *ring,
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struct amdgpu_bo *bo,
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struct reservation_object *resv,
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struct dma_fence **fence,
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bool direct);
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/*
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* sub allocation
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*/
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static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
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{
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return sa_bo->manager->gpu_addr + sa_bo->soffset;
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}
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static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
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{
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return sa_bo->manager->cpu_ptr + sa_bo->soffset;
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}
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int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager,
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unsigned size, u32 align, u32 domain);
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void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
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struct amdgpu_sa_manager *sa_manager);
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int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
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struct amdgpu_sa_bo **sa_bo,
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unsigned size, unsigned align);
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void amdgpu_sa_bo_free(struct amdgpu_device *adev,
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struct amdgpu_sa_bo **sa_bo,
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struct dma_fence *fence);
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#if defined(CONFIG_DEBUG_FS)
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void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
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struct seq_file *m);
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#endif
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#endif
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