126 lines
3.9 KiB
C
126 lines
3.9 KiB
C
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_IH_H__
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#define __AMDGPU_IH_H__
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#include <linux/chash.h>
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struct amdgpu_device;
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/*
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* vega10+ IH clients
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*/
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enum amdgpu_ih_clientid
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{
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AMDGPU_IH_CLIENTID_IH = 0x00,
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AMDGPU_IH_CLIENTID_ACP = 0x01,
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AMDGPU_IH_CLIENTID_ATHUB = 0x02,
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AMDGPU_IH_CLIENTID_BIF = 0x03,
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AMDGPU_IH_CLIENTID_DCE = 0x04,
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AMDGPU_IH_CLIENTID_ISP = 0x05,
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AMDGPU_IH_CLIENTID_PCIE0 = 0x06,
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AMDGPU_IH_CLIENTID_RLC = 0x07,
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AMDGPU_IH_CLIENTID_SDMA0 = 0x08,
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AMDGPU_IH_CLIENTID_SDMA1 = 0x09,
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AMDGPU_IH_CLIENTID_SE0SH = 0x0a,
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AMDGPU_IH_CLIENTID_SE1SH = 0x0b,
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AMDGPU_IH_CLIENTID_SE2SH = 0x0c,
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AMDGPU_IH_CLIENTID_SE3SH = 0x0d,
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AMDGPU_IH_CLIENTID_SYSHUB = 0x0e,
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AMDGPU_IH_CLIENTID_THM = 0x0f,
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AMDGPU_IH_CLIENTID_UVD = 0x10,
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AMDGPU_IH_CLIENTID_VCE0 = 0x11,
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AMDGPU_IH_CLIENTID_VMC = 0x12,
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AMDGPU_IH_CLIENTID_XDMA = 0x13,
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AMDGPU_IH_CLIENTID_GRBM_CP = 0x14,
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AMDGPU_IH_CLIENTID_ATS = 0x15,
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AMDGPU_IH_CLIENTID_ROM_SMUIO = 0x16,
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AMDGPU_IH_CLIENTID_DF = 0x17,
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AMDGPU_IH_CLIENTID_VCE1 = 0x18,
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AMDGPU_IH_CLIENTID_PWR = 0x19,
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AMDGPU_IH_CLIENTID_UTCL2 = 0x1b,
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AMDGPU_IH_CLIENTID_EA = 0x1c,
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AMDGPU_IH_CLIENTID_UTCL2LOG = 0x1d,
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AMDGPU_IH_CLIENTID_MP0 = 0x1e,
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AMDGPU_IH_CLIENTID_MP1 = 0x1f,
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AMDGPU_IH_CLIENTID_MAX,
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AMDGPU_IH_CLIENTID_VCN = AMDGPU_IH_CLIENTID_UVD
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};
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#define AMDGPU_IH_CLIENTID_LEGACY 0
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#define AMDGPU_PAGEFAULT_HASH_BITS 8
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struct amdgpu_retryfault_hashtable {
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DECLARE_CHASH_TABLE(hash, AMDGPU_PAGEFAULT_HASH_BITS, 8, 0);
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spinlock_t lock;
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int count;
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};
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/*
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* R6xx+ IH ring
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*/
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struct amdgpu_ih_ring {
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struct amdgpu_bo *ring_obj;
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volatile uint32_t *ring;
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unsigned rptr;
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unsigned ring_size;
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uint64_t gpu_addr;
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uint32_t ptr_mask;
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atomic_t lock;
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bool enabled;
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unsigned wptr_offs;
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unsigned rptr_offs;
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u32 doorbell_index;
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bool use_doorbell;
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bool use_bus_addr;
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dma_addr_t rb_dma_addr; /* only used when use_bus_addr = true */
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struct amdgpu_retryfault_hashtable *faults;
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};
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#define AMDGPU_IH_SRC_DATA_MAX_SIZE_DW 4
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struct amdgpu_iv_entry {
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unsigned client_id;
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unsigned src_id;
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unsigned ring_id;
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unsigned vm_id;
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unsigned vm_id_src;
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uint64_t timestamp;
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unsigned timestamp_src;
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unsigned pas_id;
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unsigned pasid_src;
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unsigned src_data[AMDGPU_IH_SRC_DATA_MAX_SIZE_DW];
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const uint32_t *iv_entry;
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};
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int amdgpu_ih_ring_init(struct amdgpu_device *adev, unsigned ring_size,
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bool use_bus_addr);
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void amdgpu_ih_ring_fini(struct amdgpu_device *adev);
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int amdgpu_ih_process(struct amdgpu_device *adev);
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int amdgpu_ih_add_fault(struct amdgpu_device *adev, u64 key);
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void amdgpu_ih_clear_fault(struct amdgpu_device *adev, u64 key);
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#endif
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