271 lines
6.7 KiB
C
271 lines
6.7 KiB
C
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/*
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* Copyright 2014 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "amdgpu_amdkfd.h"
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#include "amd_shared.h"
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#include <drm/drmP.h>
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#include "amdgpu.h"
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#include "amdgpu_gfx.h"
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#include <linux/module.h>
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const struct kgd2kfd_calls *kgd2kfd;
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bool (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);
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int amdgpu_amdkfd_init(void)
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{
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int ret;
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#if defined(CONFIG_HSA_AMD_MODULE)
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int (*kgd2kfd_init_p)(unsigned int, const struct kgd2kfd_calls**);
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kgd2kfd_init_p = symbol_request(kgd2kfd_init);
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if (kgd2kfd_init_p == NULL)
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return -ENOENT;
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ret = kgd2kfd_init_p(KFD_INTERFACE_VERSION, &kgd2kfd);
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if (ret) {
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symbol_put(kgd2kfd_init);
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kgd2kfd = NULL;
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}
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#elif defined(CONFIG_HSA_AMD)
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ret = kgd2kfd_init(KFD_INTERFACE_VERSION, &kgd2kfd);
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if (ret)
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kgd2kfd = NULL;
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#else
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ret = -ENOENT;
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#endif
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return ret;
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}
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void amdgpu_amdkfd_fini(void)
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{
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if (kgd2kfd) {
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kgd2kfd->exit();
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symbol_put(kgd2kfd_init);
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}
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}
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void amdgpu_amdkfd_device_probe(struct amdgpu_device *adev)
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{
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const struct kfd2kgd_calls *kfd2kgd;
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if (!kgd2kfd)
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return;
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switch (adev->asic_type) {
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#ifdef CONFIG_DRM_AMDGPU_CIK
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case CHIP_KAVERI:
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kfd2kgd = amdgpu_amdkfd_gfx_7_get_functions();
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break;
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#endif
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case CHIP_CARRIZO:
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kfd2kgd = amdgpu_amdkfd_gfx_8_0_get_functions();
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break;
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default:
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dev_info(adev->dev, "kfd not supported on this ASIC\n");
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return;
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}
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adev->kfd = kgd2kfd->probe((struct kgd_dev *)adev,
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adev->pdev, kfd2kgd);
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}
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void amdgpu_amdkfd_device_init(struct amdgpu_device *adev)
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{
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int i;
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int last_valid_bit;
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if (adev->kfd) {
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struct kgd2kfd_shared_resources gpu_resources = {
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.compute_vmid_bitmap = 0xFF00,
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.num_pipe_per_mec = adev->gfx.mec.num_pipe_per_mec,
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.num_queue_per_pipe = adev->gfx.mec.num_queue_per_pipe
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};
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/* this is going to have a few of the MSBs set that we need to
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* clear */
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bitmap_complement(gpu_resources.queue_bitmap,
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adev->gfx.mec.queue_bitmap,
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KGD_MAX_QUEUES);
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/* remove the KIQ bit as well */
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if (adev->gfx.kiq.ring.ready)
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clear_bit(amdgpu_gfx_queue_to_bit(adev,
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adev->gfx.kiq.ring.me - 1,
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adev->gfx.kiq.ring.pipe,
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adev->gfx.kiq.ring.queue),
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gpu_resources.queue_bitmap);
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/* According to linux/bitmap.h we shouldn't use bitmap_clear if
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* nbits is not compile time constant */
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last_valid_bit = 1 /* only first MEC can have compute queues */
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* adev->gfx.mec.num_pipe_per_mec
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* adev->gfx.mec.num_queue_per_pipe;
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for (i = last_valid_bit; i < KGD_MAX_QUEUES; ++i)
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clear_bit(i, gpu_resources.queue_bitmap);
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amdgpu_doorbell_get_kfd_info(adev,
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&gpu_resources.doorbell_physical_address,
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&gpu_resources.doorbell_aperture_size,
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&gpu_resources.doorbell_start_offset);
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kgd2kfd->device_init(adev->kfd, &gpu_resources);
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}
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}
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void amdgpu_amdkfd_device_fini(struct amdgpu_device *adev)
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{
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if (adev->kfd) {
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kgd2kfd->device_exit(adev->kfd);
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adev->kfd = NULL;
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}
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}
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void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev,
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const void *ih_ring_entry)
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{
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if (adev->kfd)
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kgd2kfd->interrupt(adev->kfd, ih_ring_entry);
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}
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void amdgpu_amdkfd_suspend(struct amdgpu_device *adev)
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{
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if (adev->kfd)
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kgd2kfd->suspend(adev->kfd);
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}
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int amdgpu_amdkfd_resume(struct amdgpu_device *adev)
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{
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int r = 0;
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if (adev->kfd)
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r = kgd2kfd->resume(adev->kfd);
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return r;
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}
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int alloc_gtt_mem(struct kgd_dev *kgd, size_t size,
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void **mem_obj, uint64_t *gpu_addr,
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void **cpu_ptr)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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struct kgd_mem **mem = (struct kgd_mem **) mem_obj;
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int r;
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BUG_ON(kgd == NULL);
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BUG_ON(gpu_addr == NULL);
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BUG_ON(cpu_ptr == NULL);
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*mem = kmalloc(sizeof(struct kgd_mem), GFP_KERNEL);
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if ((*mem) == NULL)
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return -ENOMEM;
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r = amdgpu_bo_create(adev, size, PAGE_SIZE, true, AMDGPU_GEM_DOMAIN_GTT,
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AMDGPU_GEM_CREATE_CPU_GTT_USWC, NULL, NULL, 0,
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&(*mem)->bo);
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if (r) {
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dev_err(adev->dev,
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"failed to allocate BO for amdkfd (%d)\n", r);
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return r;
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}
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/* map the buffer */
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r = amdgpu_bo_reserve((*mem)->bo, true);
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if (r) {
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dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
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goto allocate_mem_reserve_bo_failed;
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}
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r = amdgpu_bo_pin((*mem)->bo, AMDGPU_GEM_DOMAIN_GTT,
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&(*mem)->gpu_addr);
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if (r) {
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dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
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goto allocate_mem_pin_bo_failed;
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}
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*gpu_addr = (*mem)->gpu_addr;
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r = amdgpu_bo_kmap((*mem)->bo, &(*mem)->cpu_ptr);
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if (r) {
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dev_err(adev->dev,
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"(%d) failed to map bo to kernel for amdkfd\n", r);
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goto allocate_mem_kmap_bo_failed;
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}
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*cpu_ptr = (*mem)->cpu_ptr;
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amdgpu_bo_unreserve((*mem)->bo);
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return 0;
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allocate_mem_kmap_bo_failed:
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amdgpu_bo_unpin((*mem)->bo);
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allocate_mem_pin_bo_failed:
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amdgpu_bo_unreserve((*mem)->bo);
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allocate_mem_reserve_bo_failed:
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amdgpu_bo_unref(&(*mem)->bo);
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return r;
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}
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void free_gtt_mem(struct kgd_dev *kgd, void *mem_obj)
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{
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struct kgd_mem *mem = (struct kgd_mem *) mem_obj;
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BUG_ON(mem == NULL);
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amdgpu_bo_reserve(mem->bo, true);
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amdgpu_bo_kunmap(mem->bo);
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amdgpu_bo_unpin(mem->bo);
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amdgpu_bo_unreserve(mem->bo);
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amdgpu_bo_unref(&(mem->bo));
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kfree(mem);
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}
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uint64_t get_vmem_size(struct kgd_dev *kgd)
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{
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struct amdgpu_device *adev =
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(struct amdgpu_device *)kgd;
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BUG_ON(kgd == NULL);
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return adev->mc.real_vram_size;
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}
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uint64_t get_gpu_clock_counter(struct kgd_dev *kgd)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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if (adev->gfx.funcs->get_gpu_clock_counter)
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return adev->gfx.funcs->get_gpu_clock_counter(adev);
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return 0;
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}
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uint32_t get_max_engine_clock_in_mhz(struct kgd_dev *kgd)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
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/* The sclk is in quantas of 10kHz */
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return adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk / 100;
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}
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