434 lines
13 KiB
C
434 lines
13 KiB
C
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/*
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* GPIO driver for the WinSystems WS16C48
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* Copyright (C) 2016 William Breathitt Gray
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/errno.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/irqdesc.h>
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#include <linux/isa.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/spinlock.h>
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#define WS16C48_EXTENT 16
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#define MAX_NUM_WS16C48 max_num_isa_dev(WS16C48_EXTENT)
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static unsigned int base[MAX_NUM_WS16C48];
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static unsigned int num_ws16c48;
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module_param_hw_array(base, uint, ioport, &num_ws16c48, 0);
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MODULE_PARM_DESC(base, "WinSystems WS16C48 base addresses");
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static unsigned int irq[MAX_NUM_WS16C48];
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module_param_hw_array(irq, uint, irq, NULL, 0);
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MODULE_PARM_DESC(irq, "WinSystems WS16C48 interrupt line numbers");
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/**
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* struct ws16c48_gpio - GPIO device private data structure
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* @chip: instance of the gpio_chip
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* @io_state: bit I/O state (whether bit is set to input or output)
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* @out_state: output bits state
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* @lock: synchronization lock to prevent I/O race conditions
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* @irq_mask: I/O bits affected by interrupts
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* @flow_mask: IRQ flow type mask for the respective I/O bits
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* @base: base port address of the GPIO device
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*/
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struct ws16c48_gpio {
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struct gpio_chip chip;
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unsigned char io_state[6];
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unsigned char out_state[6];
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raw_spinlock_t lock;
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unsigned long irq_mask;
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unsigned long flow_mask;
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unsigned base;
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};
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static int ws16c48_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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return !!(ws16c48gpio->io_state[port] & mask);
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}
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static int ws16c48_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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ws16c48gpio->io_state[port] |= mask;
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ws16c48gpio->out_state[port] &= ~mask;
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outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return 0;
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}
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static int ws16c48_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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ws16c48gpio->io_state[port] &= ~mask;
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if (value)
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ws16c48gpio->out_state[port] |= mask;
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else
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ws16c48gpio->out_state[port] &= ~mask;
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outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return 0;
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}
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static int ws16c48_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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unsigned port_state;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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/* ensure that GPIO is set for input */
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if (!(ws16c48gpio->io_state[port] & mask)) {
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return -EINVAL;
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}
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port_state = inb(ws16c48gpio->base + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return !!(port_state & mask);
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}
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static void ws16c48_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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/* ensure that GPIO is set for output */
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if (ws16c48gpio->io_state[port] & mask) {
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return;
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}
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if (value)
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ws16c48gpio->out_state[port] |= mask;
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else
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ws16c48gpio->out_state[port] &= ~mask;
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outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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static void ws16c48_gpio_set_multiple(struct gpio_chip *chip,
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unsigned long *mask, unsigned long *bits)
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{
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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unsigned int i;
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const unsigned int gpio_reg_size = 8;
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unsigned int port;
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unsigned int iomask;
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unsigned int bitmask;
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unsigned long flags;
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/* set bits are evaluated a gpio register size at a time */
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for (i = 0; i < chip->ngpio; i += gpio_reg_size) {
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/* no more set bits in this mask word; skip to the next word */
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if (!mask[BIT_WORD(i)]) {
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i = (BIT_WORD(i) + 1) * BITS_PER_LONG - gpio_reg_size;
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continue;
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}
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port = i / gpio_reg_size;
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/* mask out GPIO configured for input */
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iomask = mask[BIT_WORD(i)] & ~ws16c48gpio->io_state[port];
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bitmask = iomask & bits[BIT_WORD(i)];
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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/* update output state data and set device gpio register */
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ws16c48gpio->out_state[port] &= ~iomask;
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ws16c48gpio->out_state[port] |= bitmask;
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outb(ws16c48gpio->out_state[port], ws16c48gpio->base + port);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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/* prepare for next gpio register set */
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mask[BIT_WORD(i)] >>= gpio_reg_size;
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bits[BIT_WORD(i)] >>= gpio_reg_size;
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}
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}
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static void ws16c48_irq_ack(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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const unsigned port = offset / 8;
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const unsigned mask = BIT(offset % 8);
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unsigned long flags;
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unsigned port_state;
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/* only the first 3 ports support interrupts */
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if (port > 2)
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return;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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port_state = ws16c48gpio->irq_mask >> (8*port);
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outb(0x80, ws16c48gpio->base + 7);
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outb(port_state & ~mask, ws16c48gpio->base + 8 + port);
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outb(port_state | mask, ws16c48gpio->base + 8 + port);
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outb(0xC0, ws16c48gpio->base + 7);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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static void ws16c48_irq_mask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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const unsigned long mask = BIT(offset);
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const unsigned port = offset / 8;
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unsigned long flags;
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/* only the first 3 ports support interrupts */
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if (port > 2)
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return;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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ws16c48gpio->irq_mask &= ~mask;
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outb(0x80, ws16c48gpio->base + 7);
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outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
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outb(0xC0, ws16c48gpio->base + 7);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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static void ws16c48_irq_unmask(struct irq_data *data)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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const unsigned long mask = BIT(offset);
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const unsigned port = offset / 8;
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unsigned long flags;
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/* only the first 3 ports support interrupts */
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if (port > 2)
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return;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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ws16c48gpio->irq_mask |= mask;
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outb(0x80, ws16c48gpio->base + 7);
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outb(ws16c48gpio->irq_mask >> (8*port), ws16c48gpio->base + 8 + port);
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outb(0xC0, ws16c48gpio->base + 7);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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}
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static int ws16c48_irq_set_type(struct irq_data *data, unsigned flow_type)
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{
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struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
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struct ws16c48_gpio *const ws16c48gpio = gpiochip_get_data(chip);
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const unsigned long offset = irqd_to_hwirq(data);
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const unsigned long mask = BIT(offset);
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const unsigned port = offset / 8;
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unsigned long flags;
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/* only the first 3 ports support interrupts */
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if (port > 2)
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return -EINVAL;
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raw_spin_lock_irqsave(&ws16c48gpio->lock, flags);
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switch (flow_type) {
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case IRQ_TYPE_NONE:
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break;
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case IRQ_TYPE_EDGE_RISING:
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ws16c48gpio->flow_mask |= mask;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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ws16c48gpio->flow_mask &= ~mask;
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break;
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default:
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return -EINVAL;
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}
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outb(0x40, ws16c48gpio->base + 7);
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outb(ws16c48gpio->flow_mask >> (8*port), ws16c48gpio->base + 8 + port);
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outb(0xC0, ws16c48gpio->base + 7);
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raw_spin_unlock_irqrestore(&ws16c48gpio->lock, flags);
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return 0;
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}
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static struct irq_chip ws16c48_irqchip = {
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.name = "ws16c48",
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.irq_ack = ws16c48_irq_ack,
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.irq_mask = ws16c48_irq_mask,
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.irq_unmask = ws16c48_irq_unmask,
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.irq_set_type = ws16c48_irq_set_type
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};
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static irqreturn_t ws16c48_irq_handler(int irq, void *dev_id)
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{
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struct ws16c48_gpio *const ws16c48gpio = dev_id;
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struct gpio_chip *const chip = &ws16c48gpio->chip;
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unsigned long int_pending;
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unsigned long port;
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unsigned long int_id;
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unsigned long gpio;
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int_pending = inb(ws16c48gpio->base + 6) & 0x7;
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if (!int_pending)
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return IRQ_NONE;
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/* loop until all pending interrupts are handled */
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do {
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for_each_set_bit(port, &int_pending, 3) {
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int_id = inb(ws16c48gpio->base + 8 + port);
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for_each_set_bit(gpio, &int_id, 8)
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generic_handle_irq(irq_find_mapping(
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chip->irq.domain, gpio + 8*port));
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}
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int_pending = inb(ws16c48gpio->base + 6) & 0x7;
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} while (int_pending);
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return IRQ_HANDLED;
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}
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#define WS16C48_NGPIO 48
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static const char *ws16c48_names[WS16C48_NGPIO] = {
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"Port 0 Bit 0", "Port 0 Bit 1", "Port 0 Bit 2", "Port 0 Bit 3",
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"Port 0 Bit 4", "Port 0 Bit 5", "Port 0 Bit 6", "Port 0 Bit 7",
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"Port 1 Bit 0", "Port 1 Bit 1", "Port 1 Bit 2", "Port 1 Bit 3",
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"Port 1 Bit 4", "Port 1 Bit 5", "Port 1 Bit 6", "Port 1 Bit 7",
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"Port 2 Bit 0", "Port 2 Bit 1", "Port 2 Bit 2", "Port 2 Bit 3",
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"Port 2 Bit 4", "Port 2 Bit 5", "Port 2 Bit 6", "Port 2 Bit 7",
|
||
|
|
"Port 3 Bit 0", "Port 3 Bit 1", "Port 3 Bit 2", "Port 3 Bit 3",
|
||
|
|
"Port 3 Bit 4", "Port 3 Bit 5", "Port 3 Bit 6", "Port 3 Bit 7",
|
||
|
|
"Port 4 Bit 0", "Port 4 Bit 1", "Port 4 Bit 2", "Port 4 Bit 3",
|
||
|
|
"Port 4 Bit 4", "Port 4 Bit 5", "Port 4 Bit 6", "Port 4 Bit 7",
|
||
|
|
"Port 5 Bit 0", "Port 5 Bit 1", "Port 5 Bit 2", "Port 5 Bit 3",
|
||
|
|
"Port 5 Bit 4", "Port 5 Bit 5", "Port 5 Bit 6", "Port 5 Bit 7"
|
||
|
|
};
|
||
|
|
|
||
|
|
static int ws16c48_probe(struct device *dev, unsigned int id)
|
||
|
|
{
|
||
|
|
struct ws16c48_gpio *ws16c48gpio;
|
||
|
|
const char *const name = dev_name(dev);
|
||
|
|
int err;
|
||
|
|
|
||
|
|
ws16c48gpio = devm_kzalloc(dev, sizeof(*ws16c48gpio), GFP_KERNEL);
|
||
|
|
if (!ws16c48gpio)
|
||
|
|
return -ENOMEM;
|
||
|
|
|
||
|
|
if (!devm_request_region(dev, base[id], WS16C48_EXTENT, name)) {
|
||
|
|
dev_err(dev, "Unable to lock port addresses (0x%X-0x%X)\n",
|
||
|
|
base[id], base[id] + WS16C48_EXTENT);
|
||
|
|
return -EBUSY;
|
||
|
|
}
|
||
|
|
|
||
|
|
ws16c48gpio->chip.label = name;
|
||
|
|
ws16c48gpio->chip.parent = dev;
|
||
|
|
ws16c48gpio->chip.owner = THIS_MODULE;
|
||
|
|
ws16c48gpio->chip.base = -1;
|
||
|
|
ws16c48gpio->chip.ngpio = WS16C48_NGPIO;
|
||
|
|
ws16c48gpio->chip.names = ws16c48_names;
|
||
|
|
ws16c48gpio->chip.get_direction = ws16c48_gpio_get_direction;
|
||
|
|
ws16c48gpio->chip.direction_input = ws16c48_gpio_direction_input;
|
||
|
|
ws16c48gpio->chip.direction_output = ws16c48_gpio_direction_output;
|
||
|
|
ws16c48gpio->chip.get = ws16c48_gpio_get;
|
||
|
|
ws16c48gpio->chip.set = ws16c48_gpio_set;
|
||
|
|
ws16c48gpio->chip.set_multiple = ws16c48_gpio_set_multiple;
|
||
|
|
ws16c48gpio->base = base[id];
|
||
|
|
|
||
|
|
raw_spin_lock_init(&ws16c48gpio->lock);
|
||
|
|
|
||
|
|
err = devm_gpiochip_add_data(dev, &ws16c48gpio->chip, ws16c48gpio);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "GPIO registering failed (%d)\n", err);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
/* Disable IRQ by default */
|
||
|
|
outb(0x80, base[id] + 7);
|
||
|
|
outb(0, base[id] + 8);
|
||
|
|
outb(0, base[id] + 9);
|
||
|
|
outb(0, base[id] + 10);
|
||
|
|
outb(0xC0, base[id] + 7);
|
||
|
|
|
||
|
|
err = gpiochip_irqchip_add(&ws16c48gpio->chip, &ws16c48_irqchip, 0,
|
||
|
|
handle_edge_irq, IRQ_TYPE_NONE);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "Could not add irqchip (%d)\n", err);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
err = devm_request_irq(dev, irq[id], ws16c48_irq_handler, IRQF_SHARED,
|
||
|
|
name, ws16c48gpio);
|
||
|
|
if (err) {
|
||
|
|
dev_err(dev, "IRQ handler registering failed (%d)\n", err);
|
||
|
|
return err;
|
||
|
|
}
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|
||
|
|
static struct isa_driver ws16c48_driver = {
|
||
|
|
.probe = ws16c48_probe,
|
||
|
|
.driver = {
|
||
|
|
.name = "ws16c48"
|
||
|
|
},
|
||
|
|
};
|
||
|
|
|
||
|
|
module_isa_driver(ws16c48_driver, num_ws16c48);
|
||
|
|
|
||
|
|
MODULE_AUTHOR("William Breathitt Gray <vilhelm.gray@gmail.com>");
|
||
|
|
MODULE_DESCRIPTION("WinSystems WS16C48 GPIO driver");
|
||
|
|
MODULE_LICENSE("GPL v2");
|