318 lines
7.0 KiB
C
318 lines
7.0 KiB
C
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/*
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* Xtensa hardware breakpoints/watchpoints handling functions
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2016 Cadence Design Systems Inc.
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*/
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#include <linux/hw_breakpoint.h>
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#include <linux/log2.h>
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#include <linux/percpu.h>
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#include <linux/perf_event.h>
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#include <variant/core.h>
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/* Breakpoint currently in use for each IBREAKA. */
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static DEFINE_PER_CPU(struct perf_event *, bp_on_reg[XCHAL_NUM_IBREAK]);
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/* Watchpoint currently in use for each DBREAKA. */
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static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[XCHAL_NUM_DBREAK]);
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int hw_breakpoint_slots(int type)
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{
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switch (type) {
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case TYPE_INST:
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return XCHAL_NUM_IBREAK;
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case TYPE_DATA:
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return XCHAL_NUM_DBREAK;
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default:
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pr_warn("unknown slot type: %d\n", type);
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return 0;
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}
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}
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int arch_check_bp_in_kernelspace(struct perf_event *bp)
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{
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unsigned int len;
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unsigned long va;
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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va = info->address;
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len = bp->attr.bp_len;
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return (va >= TASK_SIZE) && ((va + len - 1) >= TASK_SIZE);
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}
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/*
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* Construct an arch_hw_breakpoint from a perf_event.
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*/
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static int arch_build_bp_info(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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/* Type */
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switch (bp->attr.bp_type) {
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case HW_BREAKPOINT_X:
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info->type = XTENSA_BREAKPOINT_EXECUTE;
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break;
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case HW_BREAKPOINT_R:
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info->type = XTENSA_BREAKPOINT_LOAD;
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break;
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case HW_BREAKPOINT_W:
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info->type = XTENSA_BREAKPOINT_STORE;
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break;
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case HW_BREAKPOINT_RW:
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info->type = XTENSA_BREAKPOINT_LOAD | XTENSA_BREAKPOINT_STORE;
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break;
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default:
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return -EINVAL;
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}
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/* Len */
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info->len = bp->attr.bp_len;
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if (info->len < 1 || info->len > 64 || !is_power_of_2(info->len))
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return -EINVAL;
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/* Address */
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info->address = bp->attr.bp_addr;
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if (info->address & (info->len - 1))
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return -EINVAL;
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return 0;
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}
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int arch_validate_hwbkpt_settings(struct perf_event *bp)
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{
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int ret;
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/* Build the arch_hw_breakpoint. */
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ret = arch_build_bp_info(bp);
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return ret;
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}
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int hw_breakpoint_exceptions_notify(struct notifier_block *unused,
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unsigned long val, void *data)
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{
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return NOTIFY_DONE;
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}
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static void xtensa_wsr(unsigned long v, u8 sr)
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{
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/* We don't have indexed wsr and creating instruction dynamically
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* doesn't seem worth it given how small XCHAL_NUM_IBREAK and
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* XCHAL_NUM_DBREAK are. Thus the switch. In case build breaks here
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* the switch below needs to be extended.
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*/
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BUILD_BUG_ON(XCHAL_NUM_IBREAK > 2);
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BUILD_BUG_ON(XCHAL_NUM_DBREAK > 2);
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switch (sr) {
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#if XCHAL_NUM_IBREAK > 0
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case SREG_IBREAKA + 0:
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WSR(v, SREG_IBREAKA + 0);
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break;
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#endif
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#if XCHAL_NUM_IBREAK > 1
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case SREG_IBREAKA + 1:
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WSR(v, SREG_IBREAKA + 1);
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break;
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#endif
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#if XCHAL_NUM_DBREAK > 0
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case SREG_DBREAKA + 0:
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WSR(v, SREG_DBREAKA + 0);
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break;
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case SREG_DBREAKC + 0:
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WSR(v, SREG_DBREAKC + 0);
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break;
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#endif
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#if XCHAL_NUM_DBREAK > 1
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case SREG_DBREAKA + 1:
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WSR(v, SREG_DBREAKA + 1);
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break;
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case SREG_DBREAKC + 1:
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WSR(v, SREG_DBREAKC + 1);
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break;
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#endif
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}
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}
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static int alloc_slot(struct perf_event **slot, size_t n,
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struct perf_event *bp)
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{
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size_t i;
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for (i = 0; i < n; ++i) {
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if (!slot[i]) {
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slot[i] = bp;
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return i;
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}
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}
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return -EBUSY;
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}
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static void set_ibreak_regs(int reg, struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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unsigned long ibreakenable;
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xtensa_wsr(info->address, SREG_IBREAKA + reg);
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RSR(ibreakenable, SREG_IBREAKENABLE);
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WSR(ibreakenable | (1 << reg), SREG_IBREAKENABLE);
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}
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static void set_dbreak_regs(int reg, struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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unsigned long dbreakc = DBREAKC_MASK_MASK & -info->len;
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if (info->type & XTENSA_BREAKPOINT_LOAD)
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dbreakc |= DBREAKC_LOAD_MASK;
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if (info->type & XTENSA_BREAKPOINT_STORE)
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dbreakc |= DBREAKC_STOR_MASK;
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xtensa_wsr(info->address, SREG_DBREAKA + reg);
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xtensa_wsr(dbreakc, SREG_DBREAKC + reg);
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}
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int arch_install_hw_breakpoint(struct perf_event *bp)
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{
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int i;
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if (counter_arch_bp(bp)->type == XTENSA_BREAKPOINT_EXECUTE) {
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/* Breakpoint */
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i = alloc_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
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if (i < 0)
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return i;
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set_ibreak_regs(i, bp);
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} else {
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/* Watchpoint */
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i = alloc_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
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if (i < 0)
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return i;
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set_dbreak_regs(i, bp);
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}
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return 0;
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}
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static int free_slot(struct perf_event **slot, size_t n,
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struct perf_event *bp)
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{
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size_t i;
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for (i = 0; i < n; ++i) {
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if (slot[i] == bp) {
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slot[i] = NULL;
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return i;
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}
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}
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return -EBUSY;
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}
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void arch_uninstall_hw_breakpoint(struct perf_event *bp)
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{
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struct arch_hw_breakpoint *info = counter_arch_bp(bp);
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int i;
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if (info->type == XTENSA_BREAKPOINT_EXECUTE) {
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unsigned long ibreakenable;
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/* Breakpoint */
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i = free_slot(this_cpu_ptr(bp_on_reg), XCHAL_NUM_IBREAK, bp);
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if (i >= 0) {
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RSR(ibreakenable, SREG_IBREAKENABLE);
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WSR(ibreakenable & ~(1 << i), SREG_IBREAKENABLE);
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}
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} else {
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/* Watchpoint */
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i = free_slot(this_cpu_ptr(wp_on_reg), XCHAL_NUM_DBREAK, bp);
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if (i >= 0)
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xtensa_wsr(0, SREG_DBREAKC + i);
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}
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}
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void hw_breakpoint_pmu_read(struct perf_event *bp)
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{
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}
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void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
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{
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int i;
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struct thread_struct *t = &tsk->thread;
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for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
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if (t->ptrace_bp[i]) {
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unregister_hw_breakpoint(t->ptrace_bp[i]);
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t->ptrace_bp[i] = NULL;
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}
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}
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for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
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if (t->ptrace_wp[i]) {
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unregister_hw_breakpoint(t->ptrace_wp[i]);
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t->ptrace_wp[i] = NULL;
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}
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}
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}
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/*
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* Set ptrace breakpoint pointers to zero for this task.
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* This is required in order to prevent child processes from unregistering
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* breakpoints held by their parent.
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*/
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void clear_ptrace_hw_breakpoint(struct task_struct *tsk)
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{
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memset(tsk->thread.ptrace_bp, 0, sizeof(tsk->thread.ptrace_bp));
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memset(tsk->thread.ptrace_wp, 0, sizeof(tsk->thread.ptrace_wp));
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}
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void restore_dbreak(void)
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{
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int i;
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for (i = 0; i < XCHAL_NUM_DBREAK; ++i) {
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struct perf_event *bp = this_cpu_ptr(wp_on_reg)[i];
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if (bp)
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set_dbreak_regs(i, bp);
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}
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clear_thread_flag(TIF_DB_DISABLED);
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}
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int check_hw_breakpoint(struct pt_regs *regs)
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{
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if (regs->debugcause & BIT(DEBUGCAUSE_IBREAK_BIT)) {
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int i;
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struct perf_event **bp = this_cpu_ptr(bp_on_reg);
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for (i = 0; i < XCHAL_NUM_IBREAK; ++i) {
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if (bp[i] && !bp[i]->attr.disabled &&
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regs->pc == bp[i]->attr.bp_addr)
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perf_bp_event(bp[i], regs);
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}
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return 0;
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} else if (regs->debugcause & BIT(DEBUGCAUSE_DBREAK_BIT)) {
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struct perf_event **bp = this_cpu_ptr(wp_on_reg);
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int dbnum = (regs->debugcause & DEBUGCAUSE_DBNUM_MASK) >>
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DEBUGCAUSE_DBNUM_SHIFT;
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if (dbnum < XCHAL_NUM_DBREAK && bp[dbnum]) {
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if (user_mode(regs)) {
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perf_bp_event(bp[dbnum], regs);
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} else {
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set_thread_flag(TIF_DB_DISABLED);
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xtensa_wsr(0, SREG_DBREAKC + dbnum);
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}
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} else {
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WARN_ONCE(1,
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"Wrong/unconfigured DBNUM reported in DEBUGCAUSE: %d\n",
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dbnum);
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}
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return 0;
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}
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return -ENOENT;
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}
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