490 lines
12 KiB
ArmAsm
490 lines
12 KiB
ArmAsm
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Transactional memory support routines to reclaim and recheckpoint
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* transactional process state.
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*
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* Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
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*/
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#include <asm/asm-offsets.h>
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#include <asm/ppc_asm.h>
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#include <asm/ppc-opcode.h>
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#include <asm/ptrace.h>
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#include <asm/reg.h>
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#include <asm/bug.h>
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#ifdef CONFIG_VSX
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/* See fpu.S, this is borrowed from there */
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#define __SAVE_32FPRS_VSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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SAVE_32FPRS(n,base); \
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b 3f; \
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2: SAVE_32VSRS(n,c,base); \
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3:
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#define __REST_32FPRS_VSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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REST_32FPRS(n,base); \
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b 3f; \
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2: REST_32VSRS(n,c,base); \
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3:
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#else
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#define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
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#define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
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#endif
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#define SAVE_32FPRS_VSRS(n,c,base) \
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__SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
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#define REST_32FPRS_VSRS(n,c,base) \
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__REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
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/* Stack frame offsets for local variables. */
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#define TM_FRAME_L0 TM_FRAME_SIZE-16
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#define TM_FRAME_L1 TM_FRAME_SIZE-8
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/* In order to access the TM SPRs, TM must be enabled. So, do so: */
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_GLOBAL(tm_enable)
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mfmsr r4
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li r3, MSR_TM >> 32
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sldi r3, r3, 32
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and. r0, r4, r3
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bne 1f
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or r4, r4, r3
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mtmsrd r4
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1: blr
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_GLOBAL(tm_save_sprs)
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mfspr r0, SPRN_TFHAR
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std r0, THREAD_TM_TFHAR(r3)
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mfspr r0, SPRN_TEXASR
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std r0, THREAD_TM_TEXASR(r3)
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mfspr r0, SPRN_TFIAR
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std r0, THREAD_TM_TFIAR(r3)
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blr
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_GLOBAL(tm_restore_sprs)
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ld r0, THREAD_TM_TFHAR(r3)
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mtspr SPRN_TFHAR, r0
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ld r0, THREAD_TM_TEXASR(r3)
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mtspr SPRN_TEXASR, r0
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ld r0, THREAD_TM_TFIAR(r3)
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mtspr SPRN_TFIAR, r0
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blr
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/* Passed an 8-bit failure cause as first argument. */
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_GLOBAL(tm_abort)
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TABORT(R3)
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blr
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/* void tm_reclaim(struct thread_struct *thread,
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* uint8_t cause)
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*
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* - Performs a full reclaim. This destroys outstanding
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* transactions and updates thread->regs.tm_ckpt_* with the
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* original checkpointed state. Note that thread->regs is
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* unchanged.
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*
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* Purpose is to both abort transactions of, and preserve the state of,
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* a transactions at a context switch. We preserve/restore both sets of process
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* state to restore them when the thread's scheduled again. We continue in
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* userland as though nothing happened, but when the transaction is resumed
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* they will abort back to the checkpointed state we save out here.
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*
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* Call with IRQs off, stacks get all out of sync for some periods in here!
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*/
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_GLOBAL(tm_reclaim)
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mfcr r5
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mflr r0
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stw r5, 8(r1)
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std r0, 16(r1)
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std r2, STK_GOT(r1)
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stdu r1, -TM_FRAME_SIZE(r1)
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/* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
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std r3, STK_PARAM(R3)(r1)
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SAVE_NVGPRS(r1)
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/* We need to setup MSR for VSX register save instructions. */
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mfmsr r14
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mr r15, r14
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ori r15, r15, MSR_FP
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li r16, 0
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ori r16, r16, MSR_EE /* IRQs hard off */
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andc r15, r15, r16
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oris r15, r15, MSR_VEC@h
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r15,r15, MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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mtmsrd r15
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std r14, TM_FRAME_L0(r1)
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/* Do sanity check on MSR to make sure we are suspended */
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li r7, (MSR_TS_S)@higher
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srdi r6, r14, 32
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and r6, r6, r7
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1: tdeqi r6, 0
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EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
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/* Stash the stack pointer away for use after reclaim */
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std r1, PACAR1(r13)
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/* Clear MSR RI since we are about to change r1, EE is already off. */
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li r5, 0
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mtmsrd r5, 1
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/*
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* BE CAREFUL HERE:
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* At this point we can't take an SLB miss since we have MSR_RI
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* off. Load only to/from the stack/paca which are in SLB bolted regions
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* until we turn MSR RI back on.
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*
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* The moment we treclaim, ALL of our GPRs will switch
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* to user register state. (FPRs, CCR etc. also!)
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* Use an sprg and a tm_scratch in the PACA to shuffle.
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*/
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TRECLAIM(R4) /* Cause in r4 */
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/* ******************** GPRs ******************** */
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/* Stash the checkpointed r13 away in the scratch SPR and get the real
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* paca
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*/
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SET_SCRATCH0(r13)
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GET_PACA(r13)
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/* Stash the checkpointed r1 away in paca tm_scratch and get the real
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* stack pointer back
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*/
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std r1, PACATMSCRATCH(r13)
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ld r1, PACAR1(r13)
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/* Store the PPR in r11 and reset to decent value */
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std r11, GPR11(r1) /* Temporary stash */
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/* Reset MSR RI so we can take SLB faults again */
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li r11, MSR_RI
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mtmsrd r11, 1
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mfspr r11, SPRN_PPR
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HMT_MEDIUM
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/* Now get some more GPRS free */
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std r7, GPR7(r1) /* Temporary stash */
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std r12, GPR12(r1) /* '' '' '' */
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ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
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std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
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addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
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/* Make r7 look like an exception frame so that we
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* can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
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*/
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subi r7, r7, STACK_FRAME_OVERHEAD
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/* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
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SAVE_GPR(0, r7) /* user r0 */
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SAVE_GPR(2, r7) /* user r2 */
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SAVE_4GPRS(3, r7) /* user r3-r6 */
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SAVE_GPR(8, r7) /* user r8 */
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SAVE_GPR(9, r7) /* user r9 */
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SAVE_GPR(10, r7) /* user r10 */
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ld r3, PACATMSCRATCH(r13) /* user r1 */
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ld r4, GPR7(r1) /* user r7 */
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ld r5, GPR11(r1) /* user r11 */
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ld r6, GPR12(r1) /* user r12 */
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GET_SCRATCH0(8) /* user r13 */
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std r3, GPR1(r7)
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std r4, GPR7(r7)
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std r5, GPR11(r7)
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std r6, GPR12(r7)
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std r8, GPR13(r7)
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SAVE_NVGPRS(r7) /* user r14-r31 */
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/* ******************** NIP ******************** */
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mfspr r3, SPRN_TFHAR
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std r3, _NIP(r7) /* Returns to failhandler */
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/* The checkpointed NIP is ignored when rescheduling/rechkpting,
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* but is used in signal return to 'wind back' to the abort handler.
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*/
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/* ******************** CR,LR,CCR,MSR ********** */
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mfctr r3
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mflr r4
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mfcr r5
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mfxer r6
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std r3, _CTR(r7)
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std r4, _LINK(r7)
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std r5, _CCR(r7)
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std r6, _XER(r7)
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/* ******************** TAR, DSCR ********** */
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mfspr r3, SPRN_TAR
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mfspr r4, SPRN_DSCR
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std r3, THREAD_TM_TAR(r12)
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std r4, THREAD_TM_DSCR(r12)
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/* MSR and flags: We don't change CRs, and we don't need to alter
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* MSR.
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*/
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/* ******************** FPR/VR/VSRs ************
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* After reclaiming, capture the checkpointed FPRs/VRs.
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*
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* We enabled VEC/FP/VSX in the msr above, so we can execute these
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* instructions!
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*/
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mr r3, r12
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/* Altivec (VEC/VMX/VR)*/
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addi r7, r3, THREAD_CKVRSTATE
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SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
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mfvscr v0
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li r6, VRSTATE_VSCR
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stvx v0, r7, r6
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/* VRSAVE */
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mfspr r0, SPRN_VRSAVE
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std r0, THREAD_CKVRSAVE(r3)
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/* Floating Point (FP) */
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addi r7, r3, THREAD_CKFPSTATE
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SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
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mffs fr0
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stfd fr0,FPSTATE_FPSCR(r7)
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/* TM regs, incl TEXASR -- these live in thread_struct. Note they've
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* been updated by the treclaim, to explain to userland the failure
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* cause (aborted).
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*/
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mfspr r0, SPRN_TEXASR
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mfspr r3, SPRN_TFHAR
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mfspr r4, SPRN_TFIAR
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std r0, THREAD_TM_TEXASR(r12)
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std r3, THREAD_TM_TFHAR(r12)
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std r4, THREAD_TM_TFIAR(r12)
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/* AMR is checkpointed too, but is unsupported by Linux. */
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/* Restore original MSR/IRQ state & clear TM mode */
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ld r14, TM_FRAME_L0(r1) /* Orig MSR */
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li r15, 0
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rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
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mtmsrd r14
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REST_NVGPRS(r1)
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addi r1, r1, TM_FRAME_SIZE
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lwz r4, 8(r1)
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ld r0, 16(r1)
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mtcr r4
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mtlr r0
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ld r2, STK_GOT(r1)
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/* Load CPU's default DSCR */
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ld r0, PACA_DSCR_DEFAULT(r13)
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mtspr SPRN_DSCR, r0
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blr
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/* void __tm_recheckpoint(struct thread_struct *thread,
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* unsigned long orig_msr)
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* - Restore the checkpointed register state saved by tm_reclaim
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* when we switch_to a process.
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*
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* Call with IRQs off, stacks get all out of sync for
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* some periods in here!
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*/
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_GLOBAL(__tm_recheckpoint)
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mfcr r5
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mflr r0
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stw r5, 8(r1)
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std r0, 16(r1)
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std r2, STK_GOT(r1)
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stdu r1, -TM_FRAME_SIZE(r1)
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/* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
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* This is used for backing up the NVGPRs:
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*/
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SAVE_NVGPRS(r1)
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/* Load complete register state from ts_ckpt* registers */
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addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
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/* Make r7 look like an exception frame so that we
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* can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
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*/
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subi r7, r7, STACK_FRAME_OVERHEAD
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/* We need to setup MSR for FP/VMX/VSX register save instructions. */
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mfmsr r6
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mr r5, r6
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ori r5, r5, MSR_FP
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#ifdef CONFIG_ALTIVEC
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oris r5, r5, MSR_VEC@h
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#endif
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r5,r5, MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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mtmsrd r5
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#ifdef CONFIG_ALTIVEC
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/*
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* FP and VEC registers: These are recheckpointed from
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* thread.ckfp_state and thread.ckvr_state respectively. The
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* thread.fp_state[] version holds the 'live' (transactional)
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|
* and will be loaded subsequently by any FPUnavailable trap.
|
||
|
|
*/
|
||
|
|
addi r8, r3, THREAD_CKVRSTATE
|
||
|
|
li r5, VRSTATE_VSCR
|
||
|
|
lvx v0, r8, r5
|
||
|
|
mtvscr v0
|
||
|
|
REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
|
||
|
|
ld r5, THREAD_CKVRSAVE(r3)
|
||
|
|
mtspr SPRN_VRSAVE, r5
|
||
|
|
#endif
|
||
|
|
|
||
|
|
addi r8, r3, THREAD_CKFPSTATE
|
||
|
|
lfd fr0, FPSTATE_FPSCR(r8)
|
||
|
|
MTFSF_L(fr0)
|
||
|
|
REST_32FPRS_VSRS(0, R4, R8)
|
||
|
|
|
||
|
|
mtmsr r6 /* FP/Vec off again! */
|
||
|
|
|
||
|
|
restore_gprs:
|
||
|
|
|
||
|
|
/* ******************** CR,LR,CCR,MSR ********** */
|
||
|
|
ld r4, _CTR(r7)
|
||
|
|
ld r5, _LINK(r7)
|
||
|
|
ld r8, _XER(r7)
|
||
|
|
|
||
|
|
mtctr r4
|
||
|
|
mtlr r5
|
||
|
|
mtxer r8
|
||
|
|
|
||
|
|
/* ******************** TAR ******************** */
|
||
|
|
ld r4, THREAD_TM_TAR(r3)
|
||
|
|
mtspr SPRN_TAR, r4
|
||
|
|
|
||
|
|
/* Load up the PPR and DSCR in GPRs only at this stage */
|
||
|
|
ld r5, THREAD_TM_DSCR(r3)
|
||
|
|
ld r6, THREAD_TM_PPR(r3)
|
||
|
|
|
||
|
|
REST_GPR(0, r7) /* GPR0 */
|
||
|
|
REST_2GPRS(2, r7) /* GPR2-3 */
|
||
|
|
REST_GPR(4, r7) /* GPR4 */
|
||
|
|
REST_4GPRS(8, r7) /* GPR8-11 */
|
||
|
|
REST_2GPRS(12, r7) /* GPR12-13 */
|
||
|
|
|
||
|
|
REST_NVGPRS(r7) /* GPR14-31 */
|
||
|
|
|
||
|
|
/* Load up PPR and DSCR here so we don't run with user values for long
|
||
|
|
*/
|
||
|
|
mtspr SPRN_DSCR, r5
|
||
|
|
mtspr SPRN_PPR, r6
|
||
|
|
|
||
|
|
/* Do final sanity check on TEXASR to make sure FS is set. Do this
|
||
|
|
* here before we load up the userspace r1 so any bugs we hit will get
|
||
|
|
* a call chain */
|
||
|
|
mfspr r5, SPRN_TEXASR
|
||
|
|
srdi r5, r5, 16
|
||
|
|
li r6, (TEXASR_FS)@h
|
||
|
|
and r6, r6, r5
|
||
|
|
1: tdeqi r6, 0
|
||
|
|
EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
|
||
|
|
|
||
|
|
/* Do final sanity check on MSR to make sure we are not transactional
|
||
|
|
* or suspended
|
||
|
|
*/
|
||
|
|
mfmsr r6
|
||
|
|
li r5, (MSR_TS_MASK)@higher
|
||
|
|
srdi r6, r6, 32
|
||
|
|
and r6, r6, r5
|
||
|
|
1: tdnei r6, 0
|
||
|
|
EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
|
||
|
|
|
||
|
|
/* Restore CR */
|
||
|
|
ld r6, _CCR(r7)
|
||
|
|
mtcr r6
|
||
|
|
|
||
|
|
REST_GPR(6, r7)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Store r1 and r5 on the stack so that we can access them
|
||
|
|
* after we clear MSR RI.
|
||
|
|
*/
|
||
|
|
|
||
|
|
REST_GPR(5, r7)
|
||
|
|
std r5, -8(r1)
|
||
|
|
ld r5, GPR1(r7)
|
||
|
|
std r5, -16(r1)
|
||
|
|
|
||
|
|
REST_GPR(7, r7)
|
||
|
|
|
||
|
|
/* Clear MSR RI since we are about to change r1. EE is already off */
|
||
|
|
li r5, 0
|
||
|
|
mtmsrd r5, 1
|
||
|
|
|
||
|
|
/*
|
||
|
|
* BE CAREFUL HERE:
|
||
|
|
* At this point we can't take an SLB miss since we have MSR_RI
|
||
|
|
* off. Load only to/from the stack/paca which are in SLB bolted regions
|
||
|
|
* until we turn MSR RI back on.
|
||
|
|
*/
|
||
|
|
|
||
|
|
SET_SCRATCH0(r1)
|
||
|
|
ld r5, -8(r1)
|
||
|
|
ld r1, -16(r1)
|
||
|
|
|
||
|
|
/* Commit register state as checkpointed state: */
|
||
|
|
TRECHKPT
|
||
|
|
|
||
|
|
HMT_MEDIUM
|
||
|
|
|
||
|
|
/* Our transactional state has now changed.
|
||
|
|
*
|
||
|
|
* Now just get out of here. Transactional (current) state will be
|
||
|
|
* updated once restore is called on the return path in the _switch-ed
|
||
|
|
* -to process.
|
||
|
|
*/
|
||
|
|
|
||
|
|
GET_PACA(r13)
|
||
|
|
GET_SCRATCH0(r1)
|
||
|
|
|
||
|
|
/* R1 is restored, so we are recoverable again. EE is still off */
|
||
|
|
li r4, MSR_RI
|
||
|
|
mtmsrd r4, 1
|
||
|
|
|
||
|
|
REST_NVGPRS(r1)
|
||
|
|
|
||
|
|
addi r1, r1, TM_FRAME_SIZE
|
||
|
|
lwz r4, 8(r1)
|
||
|
|
ld r0, 16(r1)
|
||
|
|
mtcr r4
|
||
|
|
mtlr r0
|
||
|
|
ld r2, STK_GOT(r1)
|
||
|
|
|
||
|
|
/* Load CPU's default DSCR */
|
||
|
|
ld r0, PACA_DSCR_DEFAULT(r13)
|
||
|
|
mtspr SPRN_DSCR, r0
|
||
|
|
|
||
|
|
blr
|
||
|
|
|
||
|
|
/* ****************************************************************** */
|