454 lines
11 KiB
C
454 lines
11 KiB
C
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/*
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* BRIEF MODULE DESCRIPTION
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* Defines for using and allocating DMA channels on the Alchemy
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* Au1x00 MIPS processors.
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*
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* Copyright 2000, 2008 MontaVista Software Inc.
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* Author: MontaVista Software, Inc. <source@mvista.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*/
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#ifndef __ASM_AU1000_DMA_H
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#define __ASM_AU1000_DMA_H
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#include <linux/io.h> /* need byte IO */
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#include <linux/spinlock.h> /* And spinlocks */
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#include <linux/delay.h>
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#define NUM_AU1000_DMA_CHANNELS 8
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/* DMA Channel Register Offsets */
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#define DMA_MODE_SET 0x00000000
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#define DMA_MODE_READ DMA_MODE_SET
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#define DMA_MODE_CLEAR 0x00000004
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/* DMA Mode register bits follow */
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#define DMA_DAH_MASK (0x0f << 20)
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#define DMA_DID_BIT 16
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#define DMA_DID_MASK (0x0f << DMA_DID_BIT)
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#define DMA_DS (1 << 15)
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#define DMA_BE (1 << 13)
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#define DMA_DR (1 << 12)
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#define DMA_TS8 (1 << 11)
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#define DMA_DW_BIT 9
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#define DMA_DW_MASK (0x03 << DMA_DW_BIT)
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#define DMA_DW8 (0 << DMA_DW_BIT)
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#define DMA_DW16 (1 << DMA_DW_BIT)
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#define DMA_DW32 (2 << DMA_DW_BIT)
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#define DMA_NC (1 << 8)
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#define DMA_IE (1 << 7)
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#define DMA_HALT (1 << 6)
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#define DMA_GO (1 << 5)
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#define DMA_AB (1 << 4)
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#define DMA_D1 (1 << 3)
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#define DMA_BE1 (1 << 2)
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#define DMA_D0 (1 << 1)
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#define DMA_BE0 (1 << 0)
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#define DMA_PERIPHERAL_ADDR 0x00000008
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#define DMA_BUFFER0_START 0x0000000C
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#define DMA_BUFFER1_START 0x00000014
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#define DMA_BUFFER0_COUNT 0x00000010
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#define DMA_BUFFER1_COUNT 0x00000018
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#define DMA_BAH_BIT 16
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#define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
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#define DMA_COUNT_BIT 0
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#define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
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/* DMA Device IDs follow */
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enum {
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DMA_ID_UART0_TX = 0,
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DMA_ID_UART0_RX,
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DMA_ID_GP04,
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DMA_ID_GP05,
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DMA_ID_AC97C_TX,
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DMA_ID_AC97C_RX,
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DMA_ID_UART3_TX,
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DMA_ID_UART3_RX,
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DMA_ID_USBDEV_EP0_RX,
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DMA_ID_USBDEV_EP0_TX,
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DMA_ID_USBDEV_EP2_TX,
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DMA_ID_USBDEV_EP3_TX,
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DMA_ID_USBDEV_EP4_RX,
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DMA_ID_USBDEV_EP5_RX,
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DMA_ID_I2S_TX,
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DMA_ID_I2S_RX,
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DMA_NUM_DEV
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};
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/* DMA Device ID's for 2nd bank (AU1100) follow */
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enum {
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DMA_ID_SD0_TX = 0,
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DMA_ID_SD0_RX,
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DMA_ID_SD1_TX,
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DMA_ID_SD1_RX,
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DMA_NUM_DEV_BANK2
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};
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struct dma_chan {
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int dev_id; /* this channel is allocated if >= 0, */
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/* free otherwise */
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void __iomem *io;
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const char *dev_str;
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int irq;
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void *irq_dev;
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unsigned int fifo_addr;
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unsigned int mode;
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};
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/* These are in arch/mips/au1000/common/dma.c */
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extern struct dma_chan au1000_dma_table[];
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extern int request_au1000_dma(int dev_id,
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const char *dev_str,
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irq_handler_t irqhandler,
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unsigned long irqflags,
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void *irq_dev_id);
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extern void free_au1000_dma(unsigned int dmanr);
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extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
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int length, int *eof, void *data);
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extern void dump_au1000_dma_channel(unsigned int dmanr);
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extern spinlock_t au1000_dma_spin_lock;
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static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
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{
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if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
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au1000_dma_table[dmanr].dev_id < 0)
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return NULL;
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return &au1000_dma_table[dmanr];
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}
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static inline unsigned long claim_dma_lock(void)
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{
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unsigned long flags;
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spin_lock_irqsave(&au1000_dma_spin_lock, flags);
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return flags;
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}
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static inline void release_dma_lock(unsigned long flags)
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{
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spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
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}
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/*
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* Set the DMA buffer enable bits in the mode register.
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*/
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static inline void enable_dma_buffer0(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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__raw_writel(DMA_BE0, chan->io + DMA_MODE_SET);
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}
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static inline void enable_dma_buffer1(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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__raw_writel(DMA_BE1, chan->io + DMA_MODE_SET);
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}
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static inline void enable_dma_buffers(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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__raw_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
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}
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static inline void start_dma(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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__raw_writel(DMA_GO, chan->io + DMA_MODE_SET);
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}
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#define DMA_HALT_POLL 0x5000
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static inline void halt_dma(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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int i;
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if (!chan)
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return;
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__raw_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
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/* Poll the halt bit */
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for (i = 0; i < DMA_HALT_POLL; i++)
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if (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
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break;
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if (i == DMA_HALT_POLL)
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printk(KERN_INFO "halt_dma: HALT poll expired!\n");
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}
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static inline void disable_dma(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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halt_dma(dmanr);
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/* Now we can disable the buffers */
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__raw_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
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}
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static inline int dma_halted(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return 1;
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return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
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}
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/* Initialize a DMA channel. */
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static inline void init_dma(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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u32 mode;
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if (!chan)
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return;
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disable_dma(dmanr);
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/* Set device FIFO address */
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__raw_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
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mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
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if (chan->irq)
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mode |= DMA_IE;
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__raw_writel(~mode, chan->io + DMA_MODE_CLEAR);
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__raw_writel(mode, chan->io + DMA_MODE_SET);
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}
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/*
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* Set mode for a specific DMA channel
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*/
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static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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/*
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* set_dma_mode is only allowed to change endianess, direction,
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* transfer size, device FIFO width, and coherency settings.
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* Make sure anything else is masked off.
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*/
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mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
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chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
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chan->mode |= mode;
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}
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static inline unsigned int get_dma_mode(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return 0;
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return chan->mode;
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}
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static inline int get_dma_active_buffer(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return -1;
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return (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
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}
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/*
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* Set the device FIFO address for a specific DMA channel - only
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* applicable to GPO4 and GPO5. All the other devices have fixed
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* FIFO addresses.
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*/
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static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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if (chan->mode & DMA_DS) /* second bank of device IDs */
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return;
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if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
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return;
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__raw_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
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}
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/*
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* Clear the DMA buffer done bits in the mode register.
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*/
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static inline void clear_dma_done0(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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__raw_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
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}
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static inline void clear_dma_done1(unsigned int dmanr)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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__raw_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
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}
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/*
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* This does nothing - not applicable to Au1000 DMA.
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*/
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static inline void set_dma_page(unsigned int dmanr, char pagenr)
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{
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}
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/*
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* Set Buffer 0 transfer address for specific DMA channel.
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*/
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static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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__raw_writel(a, chan->io + DMA_BUFFER0_START);
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}
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/*
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* Set Buffer 1 transfer address for specific DMA channel.
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*/
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static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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__raw_writel(a, chan->io + DMA_BUFFER1_START);
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}
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/*
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* Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
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*/
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static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
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{
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struct dma_chan *chan = get_dma_chan(dmanr);
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if (!chan)
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return;
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count &= DMA_COUNT_MASK;
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__raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
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}
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/*
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* Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
|
||
|
|
*/
|
||
|
|
static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
|
||
|
|
{
|
||
|
|
struct dma_chan *chan = get_dma_chan(dmanr);
|
||
|
|
|
||
|
|
if (!chan)
|
||
|
|
return;
|
||
|
|
count &= DMA_COUNT_MASK;
|
||
|
|
__raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Set both buffer transfer sizes (max 64k) for a specific DMA channel.
|
||
|
|
*/
|
||
|
|
static inline void set_dma_count(unsigned int dmanr, unsigned int count)
|
||
|
|
{
|
||
|
|
struct dma_chan *chan = get_dma_chan(dmanr);
|
||
|
|
|
||
|
|
if (!chan)
|
||
|
|
return;
|
||
|
|
count &= DMA_COUNT_MASK;
|
||
|
|
__raw_writel(count, chan->io + DMA_BUFFER0_COUNT);
|
||
|
|
__raw_writel(count, chan->io + DMA_BUFFER1_COUNT);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Returns which buffer has its done bit set in the mode register.
|
||
|
|
* Returns -1 if neither or both done bits set.
|
||
|
|
*/
|
||
|
|
static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
|
||
|
|
{
|
||
|
|
struct dma_chan *chan = get_dma_chan(dmanr);
|
||
|
|
|
||
|
|
if (!chan)
|
||
|
|
return 0;
|
||
|
|
return __raw_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
|
||
|
|
}
|
||
|
|
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Returns the DMA channel's Buffer Done IRQ number.
|
||
|
|
*/
|
||
|
|
static inline int get_dma_done_irq(unsigned int dmanr)
|
||
|
|
{
|
||
|
|
struct dma_chan *chan = get_dma_chan(dmanr);
|
||
|
|
|
||
|
|
if (!chan)
|
||
|
|
return -1;
|
||
|
|
return chan->irq;
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Get DMA residue count. Returns the number of _bytes_ left to transfer.
|
||
|
|
*/
|
||
|
|
static inline int get_dma_residue(unsigned int dmanr)
|
||
|
|
{
|
||
|
|
int curBufCntReg, count;
|
||
|
|
struct dma_chan *chan = get_dma_chan(dmanr);
|
||
|
|
|
||
|
|
if (!chan)
|
||
|
|
return 0;
|
||
|
|
|
||
|
|
curBufCntReg = (__raw_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
|
||
|
|
DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
|
||
|
|
|
||
|
|
count = __raw_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
|
||
|
|
|
||
|
|
if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
|
||
|
|
count <<= 1;
|
||
|
|
else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
|
||
|
|
count <<= 2;
|
||
|
|
|
||
|
|
return count;
|
||
|
|
}
|
||
|
|
|
||
|
|
#endif /* __ASM_AU1000_DMA_H */
|