340 lines
7.7 KiB
C
340 lines
7.7 KiB
C
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/*
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* Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2012-2013 Xilinx, Inc.
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2006 Atmark Techno, Inc.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/sched.h>
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#include <linux/sched/clock.h>
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#include <linux/sched_clock.h>
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/timecounter.h>
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#include <asm/cpuinfo.h>
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static void __iomem *timer_baseaddr;
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static unsigned int freq_div_hz;
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static unsigned int timer_clock_freq;
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#define TCSR0 (0x00)
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#define TLR0 (0x04)
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#define TCR0 (0x08)
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#define TCSR1 (0x10)
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#define TLR1 (0x14)
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#define TCR1 (0x18)
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#define TCSR_MDT (1<<0)
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#define TCSR_UDT (1<<1)
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#define TCSR_GENT (1<<2)
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#define TCSR_CAPT (1<<3)
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#define TCSR_ARHT (1<<4)
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#define TCSR_LOAD (1<<5)
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#define TCSR_ENIT (1<<6)
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#define TCSR_ENT (1<<7)
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#define TCSR_TINT (1<<8)
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#define TCSR_PWMA (1<<9)
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#define TCSR_ENALL (1<<10)
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static unsigned int (*read_fn)(void __iomem *);
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static void (*write_fn)(u32, void __iomem *);
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static void timer_write32(u32 val, void __iomem *addr)
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{
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iowrite32(val, addr);
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}
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static unsigned int timer_read32(void __iomem *addr)
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{
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return ioread32(addr);
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}
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static void timer_write32_be(u32 val, void __iomem *addr)
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{
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iowrite32be(val, addr);
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}
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static unsigned int timer_read32_be(void __iomem *addr)
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{
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return ioread32be(addr);
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}
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static inline void xilinx_timer0_stop(void)
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{
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write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT,
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timer_baseaddr + TCSR0);
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}
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static inline void xilinx_timer0_start_periodic(unsigned long load_val)
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{
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if (!load_val)
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load_val = 1;
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/* loading value to timer reg */
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write_fn(load_val, timer_baseaddr + TLR0);
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/* load the initial value */
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write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
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/* see timer data sheet for detail
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* !ENALL - don't enable 'em all
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* !PWMA - disable pwm
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* TINT - clear interrupt status
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* ENT- enable timer itself
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* ENIT - enable interrupt
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* !LOAD - clear the bit to let go
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* ARHT - auto reload
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* !CAPT - no external trigger
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* !GENT - no external signal
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* UDT - set the timer as down counter
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* !MDT0 - generate mode
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*/
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write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
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timer_baseaddr + TCSR0);
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}
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static inline void xilinx_timer0_start_oneshot(unsigned long load_val)
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{
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if (!load_val)
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load_val = 1;
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/* loading value to timer reg */
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write_fn(load_val, timer_baseaddr + TLR0);
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/* load the initial value */
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write_fn(TCSR_LOAD, timer_baseaddr + TCSR0);
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write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT,
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timer_baseaddr + TCSR0);
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}
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static int xilinx_timer_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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pr_debug("%s: next event, delta %x\n", __func__, (u32)delta);
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xilinx_timer0_start_oneshot(delta);
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return 0;
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}
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static int xilinx_timer_shutdown(struct clock_event_device *evt)
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{
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pr_info("%s\n", __func__);
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xilinx_timer0_stop();
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return 0;
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}
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static int xilinx_timer_set_periodic(struct clock_event_device *evt)
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{
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pr_info("%s\n", __func__);
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xilinx_timer0_start_periodic(freq_div_hz);
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return 0;
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}
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static struct clock_event_device clockevent_xilinx_timer = {
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.name = "xilinx_clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_PERIODIC,
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.shift = 8,
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.rating = 300,
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.set_next_event = xilinx_timer_set_next_event,
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.set_state_shutdown = xilinx_timer_shutdown,
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.set_state_periodic = xilinx_timer_set_periodic,
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};
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static inline void timer_ack(void)
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{
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write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0);
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}
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = &clockevent_xilinx_timer;
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#ifdef CONFIG_HEART_BEAT
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microblaze_heartbeat();
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#endif
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timer_ack();
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct irqaction timer_irqaction = {
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.handler = timer_interrupt,
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.flags = IRQF_TIMER,
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.name = "timer",
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.dev_id = &clockevent_xilinx_timer,
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};
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static __init int xilinx_clockevent_init(void)
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{
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clockevent_xilinx_timer.mult =
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div_sc(timer_clock_freq, NSEC_PER_SEC,
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clockevent_xilinx_timer.shift);
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clockevent_xilinx_timer.max_delta_ns =
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clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer);
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clockevent_xilinx_timer.max_delta_ticks = (u32)~0;
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clockevent_xilinx_timer.min_delta_ns =
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clockevent_delta2ns(1, &clockevent_xilinx_timer);
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clockevent_xilinx_timer.min_delta_ticks = 1;
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clockevent_xilinx_timer.cpumask = cpumask_of(0);
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clockevents_register_device(&clockevent_xilinx_timer);
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return 0;
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}
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static u64 xilinx_clock_read(void)
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{
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return read_fn(timer_baseaddr + TCR1);
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}
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static u64 xilinx_read(struct clocksource *cs)
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{
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/* reading actual value of timer 1 */
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return (u64)xilinx_clock_read();
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}
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static struct timecounter xilinx_tc = {
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.cc = NULL,
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};
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static u64 xilinx_cc_read(const struct cyclecounter *cc)
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{
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return xilinx_read(NULL);
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}
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static struct cyclecounter xilinx_cc = {
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.read = xilinx_cc_read,
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.mask = CLOCKSOURCE_MASK(32),
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.shift = 8,
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};
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static int __init init_xilinx_timecounter(void)
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{
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xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC,
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xilinx_cc.shift);
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timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock());
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return 0;
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}
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static struct clocksource clocksource_microblaze = {
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.name = "xilinx_clocksource",
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.rating = 300,
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.read = xilinx_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static int __init xilinx_clocksource_init(void)
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{
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int ret;
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ret = clocksource_register_hz(&clocksource_microblaze,
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timer_clock_freq);
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if (ret) {
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pr_err("failed to register clocksource");
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return ret;
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}
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/* stop timer1 */
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write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT,
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timer_baseaddr + TCSR1);
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/* start timer1 - up counting without interrupt */
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write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1);
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/* register timecounter - for ftrace support */
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return init_xilinx_timecounter();
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}
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static int __init xilinx_timer_init(struct device_node *timer)
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{
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struct clk *clk;
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static int initialized;
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u32 irq;
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u32 timer_num = 1;
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int ret;
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if (initialized)
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return -EINVAL;
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initialized = 1;
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timer_baseaddr = of_iomap(timer, 0);
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if (!timer_baseaddr) {
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pr_err("ERROR: invalid timer base address\n");
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return -ENXIO;
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}
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write_fn = timer_write32;
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read_fn = timer_read32;
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write_fn(TCSR_MDT, timer_baseaddr + TCSR0);
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if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) {
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write_fn = timer_write32_be;
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read_fn = timer_read32_be;
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}
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irq = irq_of_parse_and_map(timer, 0);
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if (irq <= 0) {
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pr_err("Failed to parse and map irq");
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return -EINVAL;
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}
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of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num);
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if (timer_num) {
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pr_err("Please enable two timers in HW\n");
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return -EINVAL;
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}
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pr_info("%pOF: irq=%d\n", timer, irq);
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clk = of_clk_get(timer, 0);
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if (IS_ERR(clk)) {
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pr_err("ERROR: timer CCF input clock not found\n");
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/* If there is clock-frequency property than use it */
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of_property_read_u32(timer, "clock-frequency",
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&timer_clock_freq);
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} else {
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timer_clock_freq = clk_get_rate(clk);
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}
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if (!timer_clock_freq) {
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pr_err("ERROR: Using CPU clock frequency\n");
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timer_clock_freq = cpuinfo.cpu_clock_freq;
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}
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freq_div_hz = timer_clock_freq / HZ;
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ret = setup_irq(irq, &timer_irqaction);
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if (ret) {
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pr_err("Failed to setup IRQ");
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return ret;
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}
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#ifdef CONFIG_HEART_BEAT
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microblaze_setup_heartbeat();
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#endif
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ret = xilinx_clocksource_init();
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if (ret)
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return ret;
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ret = xilinx_clockevent_init();
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if (ret)
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return ret;
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sched_clock_register(xilinx_clock_read, 32, timer_clock_freq);
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return 0;
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}
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TIMER_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a",
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xilinx_timer_init);
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