439 lines
11 KiB
C
439 lines
11 KiB
C
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/*
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* Blackfin architecture-dependent process handling
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*
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* Copyright 2004-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later
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*/
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#include <linux/module.h>
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#include <linux/unistd.h>
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#include <linux/user.h>
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#include <linux/uaccess.h>
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#include <linux/slab.h>
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#include <linux/sched.h>
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#include <linux/sched/debug.h>
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#include <linux/sched/task.h>
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#include <linux/sched/task_stack.h>
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#include <linux/mm_types.h>
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#include <linux/tick.h>
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#include <linux/fs.h>
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#include <linux/err.h>
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#include <asm/blackfin.h>
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#include <asm/fixed_code.h>
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#include <asm/mem_map.h>
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#include <asm/irq.h>
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asmlinkage void ret_from_fork(void);
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/* Points to the SDRAM backup memory for the stack that is currently in
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* L1 scratchpad memory.
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*/
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void *current_l1_stack_save;
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/* The number of tasks currently using a L1 stack area. The SRAM is
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* allocated/deallocated whenever this changes from/to zero.
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*/
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int nr_l1stack_tasks;
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/* Start and length of the area in L1 scratchpad memory which we've allocated
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* for process stacks.
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*/
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void *l1_stack_base;
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unsigned long l1_stack_len;
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void (*pm_power_off)(void) = NULL;
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EXPORT_SYMBOL(pm_power_off);
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/*
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* The idle loop on BFIN
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*/
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#ifdef CONFIG_IDLE_L1
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void arch_cpu_idle(void)__attribute__((l1_text));
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#endif
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/*
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* This is our default idle handler. We need to disable
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* interrupts here to ensure we don't miss a wakeup call.
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*/
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void arch_cpu_idle(void)
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{
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#ifdef CONFIG_IPIPE
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ipipe_suspend_domain();
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#endif
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hard_local_irq_disable();
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if (!need_resched())
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idle_with_irq_disabled();
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hard_local_irq_enable();
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}
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#ifdef CONFIG_HOTPLUG_CPU
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void arch_cpu_idle_dead(void)
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{
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cpu_die();
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}
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#endif
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/*
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* Do necessary setup to start up a newly executed thread.
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*
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* pass the data segment into user programs if it exists,
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* it can't hurt anything as far as I can tell
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*/
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void start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
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{
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regs->pc = new_ip;
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if (current->mm)
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regs->p5 = current->mm->start_data;
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#ifndef CONFIG_SMP
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task_thread_info(current)->l1_task_info.stack_start =
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(void *)current->mm->context.stack_start;
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task_thread_info(current)->l1_task_info.lowest_sp = (void *)new_sp;
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memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info,
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sizeof(*L1_SCRATCH_TASK_INFO));
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#endif
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wrusp(new_sp);
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}
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EXPORT_SYMBOL_GPL(start_thread);
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void flush_thread(void)
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{
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}
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asmlinkage int bfin_clone(unsigned long clone_flags, unsigned long newsp)
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{
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#ifdef __ARCH_SYNC_CORE_DCACHE
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if (current->nr_cpus_allowed == num_possible_cpus())
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set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
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#endif
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if (newsp)
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newsp -= 12;
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return do_fork(clone_flags, newsp, 0, NULL, NULL);
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}
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int
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copy_thread(unsigned long clone_flags,
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unsigned long usp, unsigned long topstk,
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struct task_struct *p)
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{
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struct pt_regs *childregs;
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unsigned long *v;
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childregs = (struct pt_regs *) (task_stack_page(p) + THREAD_SIZE) - 1;
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v = ((unsigned long *)childregs) - 2;
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if (unlikely(p->flags & PF_KTHREAD)) {
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memset(childregs, 0, sizeof(struct pt_regs));
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v[0] = usp;
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v[1] = topstk;
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childregs->orig_p0 = -1;
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childregs->ipend = 0x8000;
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__asm__ __volatile__("%0 = syscfg;":"=da"(childregs->syscfg):);
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p->thread.usp = 0;
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} else {
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*childregs = *current_pt_regs();
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childregs->r0 = 0;
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p->thread.usp = usp ? : rdusp();
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v[0] = v[1] = 0;
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}
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p->thread.ksp = (unsigned long)v;
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p->thread.pc = (unsigned long)ret_from_fork;
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return 0;
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}
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unsigned long get_wchan(struct task_struct *p)
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{
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unsigned long fp, pc;
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unsigned long stack_page;
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int count = 0;
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if (!p || p == current || p->state == TASK_RUNNING)
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return 0;
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stack_page = (unsigned long)p;
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fp = p->thread.usp;
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do {
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if (fp < stack_page + sizeof(struct thread_info) ||
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fp >= 8184 + stack_page)
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return 0;
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pc = ((unsigned long *)fp)[1];
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if (!in_sched_functions(pc))
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return pc;
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fp = *(unsigned long *)fp;
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}
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while (count++ < 16);
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return 0;
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}
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void finish_atomic_sections (struct pt_regs *regs)
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{
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int __user *up0 = (int __user *)regs->p0;
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switch (regs->pc) {
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default:
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/* not in middle of an atomic step, so resume like normal */
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return;
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case ATOMIC_XCHG32 + 2:
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put_user(regs->r1, up0);
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break;
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case ATOMIC_CAS32 + 2:
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case ATOMIC_CAS32 + 4:
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if (regs->r0 == regs->r1)
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case ATOMIC_CAS32 + 6:
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put_user(regs->r2, up0);
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break;
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case ATOMIC_ADD32 + 2:
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regs->r0 = regs->r1 + regs->r0;
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/* fall through */
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case ATOMIC_ADD32 + 4:
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put_user(regs->r0, up0);
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break;
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case ATOMIC_SUB32 + 2:
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regs->r0 = regs->r1 - regs->r0;
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/* fall through */
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case ATOMIC_SUB32 + 4:
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put_user(regs->r0, up0);
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break;
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case ATOMIC_IOR32 + 2:
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regs->r0 = regs->r1 | regs->r0;
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/* fall through */
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case ATOMIC_IOR32 + 4:
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put_user(regs->r0, up0);
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break;
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case ATOMIC_AND32 + 2:
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regs->r0 = regs->r1 & regs->r0;
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/* fall through */
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case ATOMIC_AND32 + 4:
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put_user(regs->r0, up0);
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break;
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case ATOMIC_XOR32 + 2:
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regs->r0 = regs->r1 ^ regs->r0;
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/* fall through */
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case ATOMIC_XOR32 + 4:
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put_user(regs->r0, up0);
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break;
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}
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/*
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* We've finished the atomic section, and the only thing left for
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* userspace is to do a RTS, so we might as well handle that too
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* since we need to update the PC anyways.
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*/
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regs->pc = regs->rets;
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}
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static inline
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int in_mem(unsigned long addr, unsigned long size,
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unsigned long start, unsigned long end)
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{
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return addr >= start && addr + size <= end;
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}
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static inline
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int in_mem_const_off(unsigned long addr, unsigned long size, unsigned long off,
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unsigned long const_addr, unsigned long const_size)
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{
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return const_size &&
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in_mem(addr, size, const_addr + off, const_addr + const_size);
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}
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static inline
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int in_mem_const(unsigned long addr, unsigned long size,
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unsigned long const_addr, unsigned long const_size)
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{
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return in_mem_const_off(addr, size, 0, const_addr, const_size);
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}
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#ifdef CONFIG_BF60x
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#define ASYNC_ENABLED(bnum, bctlnum) 1
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#else
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#define ASYNC_ENABLED(bnum, bctlnum) \
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({ \
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(bfin_read_EBIU_AMGCTL() & 0xe) < ((bnum + 1) << 1) ? 0 : \
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bfin_read_EBIU_AMBCTL##bctlnum() & B##bnum##RDYEN ? 0 : \
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1; \
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})
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#endif
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/*
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* We can't read EBIU banks that aren't enabled or we end up hanging
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* on the access to the async space. Make sure we validate accesses
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* that cross async banks too.
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* 0 - found, but unusable
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* 1 - found & usable
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* 2 - not found
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*/
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static
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int in_async(unsigned long addr, unsigned long size)
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{
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if (addr >= ASYNC_BANK0_BASE && addr < ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE) {
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if (!ASYNC_ENABLED(0, 0))
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return 0;
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if (addr + size <= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE)
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return 1;
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size -= ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE - addr;
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addr = ASYNC_BANK0_BASE + ASYNC_BANK0_SIZE;
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}
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if (addr >= ASYNC_BANK1_BASE && addr < ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE) {
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if (!ASYNC_ENABLED(1, 0))
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return 0;
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if (addr + size <= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE)
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return 1;
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size -= ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE - addr;
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addr = ASYNC_BANK1_BASE + ASYNC_BANK1_SIZE;
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}
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if (addr >= ASYNC_BANK2_BASE && addr < ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE) {
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if (!ASYNC_ENABLED(2, 1))
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return 0;
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if (addr + size <= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE)
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return 1;
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size -= ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE - addr;
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addr = ASYNC_BANK2_BASE + ASYNC_BANK2_SIZE;
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}
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if (addr >= ASYNC_BANK3_BASE && addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE) {
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if (ASYNC_ENABLED(3, 1))
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return 0;
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if (addr + size <= ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)
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return 1;
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return 0;
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}
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/* not within async bounds */
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return 2;
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}
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int bfin_mem_access_type(unsigned long addr, unsigned long size)
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{
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int cpu = raw_smp_processor_id();
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/* Check that things do not wrap around */
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if (addr > ULONG_MAX - size)
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return -EFAULT;
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if (in_mem(addr, size, FIXED_CODE_START, physical_mem_end))
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return BFIN_MEM_ACCESS_CORE;
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if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
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return cpu == 0 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
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if (in_mem_const(addr, size, L1_SCRATCH_START, L1_SCRATCH_LENGTH))
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return cpu == 0 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
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if (in_mem_const(addr, size, L1_DATA_A_START, L1_DATA_A_LENGTH))
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return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
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if (in_mem_const(addr, size, L1_DATA_B_START, L1_DATA_B_LENGTH))
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return cpu == 0 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
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#ifdef COREB_L1_CODE_START
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if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
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return cpu == 1 ? BFIN_MEM_ACCESS_ITEST : BFIN_MEM_ACCESS_IDMA;
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if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
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return cpu == 1 ? BFIN_MEM_ACCESS_CORE_ONLY : -EFAULT;
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if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
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return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
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if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
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return cpu == 1 ? BFIN_MEM_ACCESS_CORE : BFIN_MEM_ACCESS_IDMA;
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#endif
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if (in_mem_const(addr, size, L2_START, L2_LENGTH))
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return BFIN_MEM_ACCESS_CORE;
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if (addr >= SYSMMR_BASE)
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return BFIN_MEM_ACCESS_CORE_ONLY;
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switch (in_async(addr, size)) {
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case 0: return -EFAULT;
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case 1: return BFIN_MEM_ACCESS_CORE;
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case 2: /* fall through */;
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}
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if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
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return BFIN_MEM_ACCESS_CORE;
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if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
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return BFIN_MEM_ACCESS_DMA;
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|
|
return -EFAULT;
|
||
|
|
}
|
||
|
|
|
||
|
|
#if defined(CONFIG_ACCESS_CHECK)
|
||
|
|
#ifdef CONFIG_ACCESS_OK_L1
|
||
|
|
__attribute__((l1_text))
|
||
|
|
#endif
|
||
|
|
/* Return 1 if access to memory range is OK, 0 otherwise */
|
||
|
|
int _access_ok(unsigned long addr, unsigned long size)
|
||
|
|
{
|
||
|
|
int aret;
|
||
|
|
|
||
|
|
if (size == 0)
|
||
|
|
return 1;
|
||
|
|
/* Check that things do not wrap around */
|
||
|
|
if (addr > ULONG_MAX - size)
|
||
|
|
return 0;
|
||
|
|
if (uaccess_kernel())
|
||
|
|
return 1;
|
||
|
|
#ifdef CONFIG_MTD_UCLINUX
|
||
|
|
if (1)
|
||
|
|
#else
|
||
|
|
if (0)
|
||
|
|
#endif
|
||
|
|
{
|
||
|
|
if (in_mem(addr, size, memory_start, memory_end))
|
||
|
|
return 1;
|
||
|
|
if (in_mem(addr, size, memory_mtd_end, physical_mem_end))
|
||
|
|
return 1;
|
||
|
|
# ifndef CONFIG_ROMFS_ON_MTD
|
||
|
|
if (0)
|
||
|
|
# endif
|
||
|
|
/* For XIP, allow user space to use pointers within the ROMFS. */
|
||
|
|
if (in_mem(addr, size, memory_mtd_start, memory_mtd_end))
|
||
|
|
return 1;
|
||
|
|
} else {
|
||
|
|
if (in_mem(addr, size, memory_start, physical_mem_end))
|
||
|
|
return 1;
|
||
|
|
}
|
||
|
|
|
||
|
|
if (in_mem(addr, size, (unsigned long)__init_begin, (unsigned long)__init_end))
|
||
|
|
return 1;
|
||
|
|
|
||
|
|
if (in_mem_const(addr, size, L1_CODE_START, L1_CODE_LENGTH))
|
||
|
|
return 1;
|
||
|
|
if (in_mem_const_off(addr, size, _etext_l1 - _stext_l1, L1_CODE_START, L1_CODE_LENGTH))
|
||
|
|
return 1;
|
||
|
|
if (in_mem_const_off(addr, size, _ebss_l1 - _sdata_l1, L1_DATA_A_START, L1_DATA_A_LENGTH))
|
||
|
|
return 1;
|
||
|
|
if (in_mem_const_off(addr, size, _ebss_b_l1 - _sdata_b_l1, L1_DATA_B_START, L1_DATA_B_LENGTH))
|
||
|
|
return 1;
|
||
|
|
#ifdef COREB_L1_CODE_START
|
||
|
|
if (in_mem_const(addr, size, COREB_L1_CODE_START, COREB_L1_CODE_LENGTH))
|
||
|
|
return 1;
|
||
|
|
if (in_mem_const(addr, size, COREB_L1_SCRATCH_START, L1_SCRATCH_LENGTH))
|
||
|
|
return 1;
|
||
|
|
if (in_mem_const(addr, size, COREB_L1_DATA_A_START, COREB_L1_DATA_A_LENGTH))
|
||
|
|
return 1;
|
||
|
|
if (in_mem_const(addr, size, COREB_L1_DATA_B_START, COREB_L1_DATA_B_LENGTH))
|
||
|
|
return 1;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#ifndef CONFIG_EXCEPTION_L1_SCRATCH
|
||
|
|
if (in_mem_const(addr, size, (unsigned long)l1_stack_base, l1_stack_len))
|
||
|
|
return 1;
|
||
|
|
#endif
|
||
|
|
|
||
|
|
aret = in_async(addr, size);
|
||
|
|
if (aret < 2)
|
||
|
|
return aret;
|
||
|
|
|
||
|
|
if (in_mem_const_off(addr, size, _ebss_l2 - _stext_l2, L2_START, L2_LENGTH))
|
||
|
|
return 1;
|
||
|
|
|
||
|
|
if (in_mem_const(addr, size, BOOT_ROM_START, BOOT_ROM_LENGTH))
|
||
|
|
return 1;
|
||
|
|
if (in_mem_const(addr, size, L1_ROM_START, L1_ROM_LENGTH))
|
||
|
|
return 1;
|
||
|
|
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
EXPORT_SYMBOL(_access_ok);
|
||
|
|
#endif /* CONFIG_ACCESS_CHECK */
|