103 lines
2.7 KiB
C
103 lines
2.7 KiB
C
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/*
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* Blackfin CPLB initialization
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*
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* Copyright 2008-2009 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#include <linux/module.h>
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#include <asm/blackfin.h>
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#include <asm/cplb.h>
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#include <asm/cplbinit.h>
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#include <asm/mem_map.h>
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struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
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struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
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int first_switched_icplb, first_switched_dcplb;
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int first_mask_dcplb;
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void __init generate_cplb_tables_cpu(unsigned int cpu)
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{
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int i_d, i_i;
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unsigned long addr;
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unsigned long d_data, i_data;
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unsigned long d_cache = 0, i_cache = 0;
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printk(KERN_INFO "MPU: setting up cplb tables with memory protection\n");
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#ifdef CONFIG_BFIN_EXTMEM_ICACHEABLE
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i_cache = CPLB_L1_CHBL | ANOMALY_05000158_WORKAROUND;
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#endif
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#ifdef CONFIG_BFIN_EXTMEM_DCACHEABLE
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d_cache = CPLB_L1_CHBL;
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#ifdef CONFIG_BFIN_EXTMEM_WRITETHROUGH
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d_cache |= CPLB_L1_AOW | CPLB_WT;
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#endif
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#endif
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i_d = i_i = 0;
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/* Set up the zero page. */
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dcplb_tbl[cpu][i_d].addr = 0;
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dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
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icplb_tbl[cpu][i_i].addr = 0;
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icplb_tbl[cpu][i_i++].data = CPLB_VALID | i_cache | CPLB_USER_RD | PAGE_SIZE_1KB;
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/* Cover kernel memory with 4M pages. */
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addr = 0;
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d_data = d_cache | CPLB_SUPV_WR | CPLB_VALID | PAGE_SIZE_4MB | CPLB_DIRTY;
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i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
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for (; addr < memory_start; addr += 4 * 1024 * 1024) {
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dcplb_tbl[cpu][i_d].addr = addr;
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dcplb_tbl[cpu][i_d++].data = d_data;
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icplb_tbl[cpu][i_i].addr = addr;
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icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
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}
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#ifdef CONFIG_ROMKERNEL
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/* Cover kernel XIP flash area */
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addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
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dcplb_tbl[cpu][i_d].addr = addr;
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dcplb_tbl[cpu][i_d++].data = d_data | CPLB_USER_RD;
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icplb_tbl[cpu][i_i].addr = addr;
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icplb_tbl[cpu][i_i++].data = i_data | CPLB_USER_RD;
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#endif
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/* Cover L1 memory. One 4M area for code and data each is enough. */
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#if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
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dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
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dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
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#endif
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#if L1_CODE_LENGTH > 0
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icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
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icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
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#endif
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/* Cover L2 memory */
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#if L2_LENGTH > 0
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dcplb_tbl[cpu][i_d].addr = L2_START;
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dcplb_tbl[cpu][i_d++].data = L2_DMEMORY;
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icplb_tbl[cpu][i_i].addr = L2_START;
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icplb_tbl[cpu][i_i++].data = L2_IMEMORY;
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#endif
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first_mask_dcplb = i_d;
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first_switched_dcplb = i_d + (1 << page_mask_order);
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first_switched_icplb = i_i;
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while (i_d < MAX_CPLBS)
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dcplb_tbl[cpu][i_d++].data = 0;
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while (i_i < MAX_CPLBS)
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icplb_tbl[cpu][i_i++].data = 0;
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}
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void __init generate_cplb_tables_all(void)
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{
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}
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