215 lines
6.3 KiB
C
215 lines
6.3 KiB
C
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/*
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* bfin_twi.h - interface to Blackfin TWIs
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*
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* Copyright 2005-2014 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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#ifndef __ASM_BFIN_TWI_H__
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#define __ASM_BFIN_TWI_H__
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#include <asm/blackfin.h>
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#include <linux/types.h>
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#include <linux/i2c.h>
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/*
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* ADI twi registers layout
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*/
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struct bfin_twi_regs {
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u16 clkdiv;
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u16 dummy1;
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u16 control;
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u16 dummy2;
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u16 slave_ctl;
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u16 dummy3;
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u16 slave_stat;
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u16 dummy4;
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u16 slave_addr;
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u16 dummy5;
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u16 master_ctl;
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u16 dummy6;
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u16 master_stat;
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u16 dummy7;
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u16 master_addr;
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u16 dummy8;
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u16 int_stat;
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u16 dummy9;
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u16 int_mask;
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u16 dummy10;
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u16 fifo_ctl;
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u16 dummy11;
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u16 fifo_stat;
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u16 dummy12;
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u32 __pad[20];
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u16 xmt_data8;
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u16 dummy13;
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u16 xmt_data16;
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u16 dummy14;
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u16 rcv_data8;
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u16 dummy15;
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u16 rcv_data16;
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u16 dummy16;
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};
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struct bfin_twi_iface {
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int irq;
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spinlock_t lock;
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char read_write;
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u8 command;
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u8 *transPtr;
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int readNum;
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int writeNum;
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int cur_mode;
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int manual_stop;
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int result;
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struct i2c_adapter adap;
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struct completion complete;
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struct i2c_msg *pmsg;
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int msg_num;
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int cur_msg;
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u16 saved_clkdiv;
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u16 saved_control;
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struct bfin_twi_regs __iomem *regs_base;
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};
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/* ******************** TWO-WIRE INTERFACE (TWI) MASKS ********************/
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/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y); ) */
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#define CLKLOW(x) ((x) & 0xFF) /* Periods Clock Is Held Low */
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#define CLKHI(y) (((y)&0xFF)<<0x8) /* Periods Before New Clock Low */
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/* TWI_PRESCALE Masks */
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#define PRESCALE 0x007F /* SCLKs Per Internal Time Reference (10MHz) */
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#define TWI_ENA 0x0080 /* TWI Enable */
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#define SCCB 0x0200 /* SCCB Compatibility Enable */
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/* TWI_SLAVE_CTL Masks */
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#define SEN 0x0001 /* Slave Enable */
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#define SADD_LEN 0x0002 /* Slave Address Length */
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#define STDVAL 0x0004 /* Slave Transmit Data Valid */
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#define NAK 0x0008 /* NAK Generated At Conclusion Of Transfer */
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#define GEN 0x0010 /* General Call Address Matching Enabled */
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/* TWI_SLAVE_STAT Masks */
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#define SDIR 0x0001 /* Slave Transfer Direction (RX/TX*) */
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#define GCALL 0x0002 /* General Call Indicator */
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/* TWI_MASTER_CTL Masks */
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#define MEN 0x0001 /* Master Mode Enable */
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#define MADD_LEN 0x0002 /* Master Address Length */
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#define MDIR 0x0004 /* Master Transmit Direction (RX/TX*) */
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#define FAST 0x0008 /* Use Fast Mode Timing Specs */
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#define STOP 0x0010 /* Issue Stop Condition */
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#define RSTART 0x0020 /* Repeat Start or Stop* At End Of Transfer */
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#define DCNT 0x3FC0 /* Data Bytes To Transfer */
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#define SDAOVR 0x4000 /* Serial Data Override */
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#define SCLOVR 0x8000 /* Serial Clock Override */
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/* TWI_MASTER_STAT Masks */
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#define MPROG 0x0001 /* Master Transfer In Progress */
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#define LOSTARB 0x0002 /* Lost Arbitration Indicator (Xfer Aborted) */
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#define ANAK 0x0004 /* Address Not Acknowledged */
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#define DNAK 0x0008 /* Data Not Acknowledged */
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#define BUFRDERR 0x0010 /* Buffer Read Error */
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#define BUFWRERR 0x0020 /* Buffer Write Error */
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#define SDASEN 0x0040 /* Serial Data Sense */
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#define SCLSEN 0x0080 /* Serial Clock Sense */
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#define BUSBUSY 0x0100 /* Bus Busy Indicator */
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/* TWI_INT_SRC and TWI_INT_ENABLE Masks */
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#define SINIT 0x0001 /* Slave Transfer Initiated */
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#define SCOMP 0x0002 /* Slave Transfer Complete */
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#define SERR 0x0004 /* Slave Transfer Error */
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#define SOVF 0x0008 /* Slave Overflow */
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#define MCOMP 0x0010 /* Master Transfer Complete */
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#define MERR 0x0020 /* Master Transfer Error */
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#define XMTSERV 0x0040 /* Transmit FIFO Service */
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#define RCVSERV 0x0080 /* Receive FIFO Service */
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/* TWI_FIFO_CTRL Masks */
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#define XMTFLUSH 0x0001 /* Transmit Buffer Flush */
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#define RCVFLUSH 0x0002 /* Receive Buffer Flush */
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#define XMTINTLEN 0x0004 /* Transmit Buffer Interrupt Length */
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#define RCVINTLEN 0x0008 /* Receive Buffer Interrupt Length */
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/* TWI_FIFO_STAT Masks */
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#define XMTSTAT 0x0003 /* Transmit FIFO Status */
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#define XMT_EMPTY 0x0000 /* Transmit FIFO Empty */
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#define XMT_HALF 0x0001 /* Transmit FIFO Has 1 Byte To Write */
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#define XMT_FULL 0x0003 /* Transmit FIFO Full (2 Bytes To Write) */
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#define RCVSTAT 0x000C /* Receive FIFO Status */
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#define RCV_EMPTY 0x0000 /* Receive FIFO Empty */
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#define RCV_HALF 0x0004 /* Receive FIFO Has 1 Byte To Read */
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#define RCV_FULL 0x000C /* Receive FIFO Full (2 Bytes To Read) */
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#define DEFINE_TWI_REG(reg_name, reg) \
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static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
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{ return bfin_read16(&iface->regs_base->reg); } \
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static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
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{ bfin_write16(&iface->regs_base->reg, v); }
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DEFINE_TWI_REG(CLKDIV, clkdiv)
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DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
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DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
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DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
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DEFINE_TWI_REG(MASTER_CTL, master_ctl)
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DEFINE_TWI_REG(MASTER_STAT, master_stat)
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DEFINE_TWI_REG(MASTER_ADDR, master_addr)
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DEFINE_TWI_REG(INT_STAT, int_stat)
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DEFINE_TWI_REG(INT_MASK, int_mask)
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DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
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DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
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DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
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#if !ANOMALY_16000030
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DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
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DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
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#else
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static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
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{
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u16 ret;
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unsigned long flags;
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flags = hard_local_irq_save();
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ret = bfin_read16(&iface->regs_base->rcv_data8);
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hard_local_irq_restore(flags);
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return ret;
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}
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static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
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{
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u16 ret;
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unsigned long flags;
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flags = hard_local_irq_save();
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ret = bfin_read16(&iface->regs_base->rcv_data16);
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hard_local_irq_restore(flags);
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return ret;
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}
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#endif
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static inline u16 read_FIFO_CTL(struct bfin_twi_iface *iface)
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{
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return bfin_read16(&iface->regs_base->fifo_ctl);
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}
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static inline void write_FIFO_CTL(struct bfin_twi_iface *iface, u16 v)
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{
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bfin_write16(&iface->regs_base->fifo_ctl, v);
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SSYNC();
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}
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static inline u16 read_CONTROL(struct bfin_twi_iface *iface)
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{
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return bfin_read16(&iface->regs_base->control);
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}
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static inline void write_CONTROL(struct bfin_twi_iface *iface, u16 v)
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{
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SSYNC();
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bfin_write16(&iface->regs_base->control, v);
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}
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#endif
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