598 lines
15 KiB
Plaintext
598 lines
15 KiB
Plaintext
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/*
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* Copyright (C) 2016 ARM Ltd.
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* based on the Allwinner H3 dtsi:
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* Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/sun50i-a64-ccu.h>
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#include <dt-bindings/clock/sun8i-r-ccu.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/sun50i-a64-ccu.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <0>;
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enable-method = "psci";
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};
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cpu1: cpu@1 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <1>;
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enable-method = "psci";
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};
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cpu2: cpu@2 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <2>;
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enable-method = "psci";
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};
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cpu3: cpu@3 {
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compatible = "arm,cortex-a53", "arm,armv8";
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device_type = "cpu";
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reg = <3>;
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enable-method = "psci";
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};
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};
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osc24M: osc24M_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "osc24M";
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};
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osc32k: osc32k_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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clock-output-names = "osc32k";
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};
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iosc: internal-osc-clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <16000000>;
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clock-accuracy = <300000000>;
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clock-output-names = "iosc";
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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syscon: syscon@1c00000 {
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compatible = "allwinner,sun50i-a64-system-controller",
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"syscon";
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reg = <0x01c00000 0x1000>;
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};
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dma: dma-controller@1c02000 {
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compatible = "allwinner,sun50i-a64-dma";
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reg = <0x01c02000 0x1000>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_DMA>;
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dma-channels = <8>;
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dma-requests = <27>;
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resets = <&ccu RST_BUS_DMA>;
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#dma-cells = <1>;
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun50i-a64-mmc";
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reg = <0x01c0f000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC0>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <150000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc1: mmc@1c10000 {
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compatible = "allwinner,sun50i-a64-mmc";
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reg = <0x01c10000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC1>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <150000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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mmc2: mmc@1c11000 {
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compatible = "allwinner,sun50i-a64-emmc";
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reg = <0x01c11000 0x1000>;
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clocks = <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>;
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clock-names = "ahb", "mmc";
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resets = <&ccu RST_BUS_MMC2>;
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reset-names = "ahb";
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interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
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max-frequency = <200000000>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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};
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usb_otg: usb@1c19000 {
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compatible = "allwinner,sun8i-a33-musb";
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reg = <0x01c19000 0x0400>;
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clocks = <&ccu CLK_BUS_OTG>;
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resets = <&ccu RST_BUS_OTG>;
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "mc";
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phys = <&usbphy 0>;
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phy-names = "usb";
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extcon = <&usbphy 0>;
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status = "disabled";
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};
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usbphy: phy@1c19400 {
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compatible = "allwinner,sun50i-a64-usb-phy";
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reg = <0x01c19400 0x14>,
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<0x01c1a800 0x4>,
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<0x01c1b800 0x4>;
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reg-names = "phy_ctrl",
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"pmu0",
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"pmu1";
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clocks = <&ccu CLK_USB_PHY0>,
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<&ccu CLK_USB_PHY1>;
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clock-names = "usb0_phy",
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"usb1_phy";
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resets = <&ccu RST_USB_PHY0>,
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<&ccu RST_USB_PHY1>;
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reset-names = "usb0_reset",
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"usb1_reset";
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status = "disabled";
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#phy-cells = <1>;
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};
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ehci0: usb@1c1a000 {
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compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
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reg = <0x01c1a000 0x100>;
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interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI0>,
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<&ccu CLK_BUS_EHCI0>,
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<&ccu CLK_USB_OHCI0>;
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resets = <&ccu RST_BUS_OHCI0>,
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<&ccu RST_BUS_EHCI0>;
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status = "disabled";
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};
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ohci0: usb@1c1a400 {
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compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
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reg = <0x01c1a400 0x100>;
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interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI0>,
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<&ccu CLK_USB_OHCI0>;
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resets = <&ccu RST_BUS_OHCI0>;
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status = "disabled";
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};
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ehci1: usb@1c1b000 {
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compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
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reg = <0x01c1b000 0x100>;
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interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI1>,
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<&ccu CLK_BUS_EHCI1>,
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<&ccu CLK_USB_OHCI1>;
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resets = <&ccu RST_BUS_OHCI1>,
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<&ccu RST_BUS_EHCI1>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ohci1: usb@1c1b400 {
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compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
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reg = <0x01c1b400 0x100>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_OHCI1>,
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<&ccu CLK_USB_OHCI1>;
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resets = <&ccu RST_BUS_OHCI1>;
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phys = <&usbphy 1>;
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phy-names = "usb";
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status = "disabled";
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};
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ccu: clock@1c20000 {
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compatible = "allwinner,sun50i-a64-ccu";
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reg = <0x01c20000 0x400>;
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clocks = <&osc24M>, <&osc32k>;
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clock-names = "hosc", "losc";
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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pio: pinctrl@1c20800 {
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compatible = "allwinner,sun50i-a64-pinctrl";
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reg = <0x01c20800 0x400>;
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interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu 58>;
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gpio-controller;
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#gpio-cells = <3>;
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interrupt-controller;
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#interrupt-cells = <3>;
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i2c1_pins: i2c1_pins {
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pins = "PH2", "PH3";
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function = "i2c1";
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};
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mmc0_pins: mmc0-pins {
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pins = "PF0", "PF1", "PF2", "PF3",
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"PF4", "PF5";
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function = "mmc0";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc1_pins: mmc1-pins {
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pins = "PG0", "PG1", "PG2", "PG3",
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"PG4", "PG5";
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function = "mmc1";
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drive-strength = <30>;
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bias-pull-up;
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};
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mmc2_pins: mmc2-pins {
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pins = "PC1", "PC5", "PC6", "PC8", "PC9",
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"PC10","PC11", "PC12", "PC13",
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"PC14", "PC15", "PC16";
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function = "mmc2";
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drive-strength = <30>;
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bias-pull-up;
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};
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rmii_pins: rmii_pins {
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pins = "PD10", "PD11", "PD13", "PD14", "PD17",
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"PD18", "PD19", "PD20", "PD22", "PD23";
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function = "emac";
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drive-strength = <40>;
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};
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rgmii_pins: rgmii_pins {
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pins = "PD8", "PD9", "PD10", "PD11", "PD12",
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"PD13", "PD15", "PD16", "PD17", "PD18",
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"PD19", "PD20", "PD21", "PD22", "PD23";
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function = "emac";
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drive-strength = <40>;
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};
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spi0_pins: spi0 {
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pins = "PC0", "PC1", "PC2", "PC3";
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function = "spi0";
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};
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spi1_pins: spi1 {
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pins = "PD0", "PD1", "PD2", "PD3";
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function = "spi1";
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};
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uart0_pins_a: uart0 {
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pins = "PB8", "PB9";
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function = "uart0";
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};
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uart1_pins: uart1_pins {
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|
|
pins = "PG6", "PG7";
|
||
|
|
function = "uart1";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart1_rts_cts_pins: uart1_rts_cts_pins {
|
||
|
|
pins = "PG8", "PG9";
|
||
|
|
function = "uart1";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart2_pins: uart2-pins {
|
||
|
|
pins = "PB0", "PB1";
|
||
|
|
function = "uart2";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart3_pins: uart3-pins {
|
||
|
|
pins = "PD0", "PD1";
|
||
|
|
function = "uart3";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart4_pins: uart4-pins {
|
||
|
|
pins = "PD2", "PD3";
|
||
|
|
function = "uart4";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart4_rts_cts_pins: uart4-rts-cts-pins {
|
||
|
|
pins = "PD4", "PD5";
|
||
|
|
function = "uart4";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
uart0: serial@1c28000 {
|
||
|
|
compatible = "snps,dw-apb-uart";
|
||
|
|
reg = <0x01c28000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg-shift = <2>;
|
||
|
|
reg-io-width = <4>;
|
||
|
|
clocks = <&ccu CLK_BUS_UART0>;
|
||
|
|
resets = <&ccu RST_BUS_UART0>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart1: serial@1c28400 {
|
||
|
|
compatible = "snps,dw-apb-uart";
|
||
|
|
reg = <0x01c28400 0x400>;
|
||
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg-shift = <2>;
|
||
|
|
reg-io-width = <4>;
|
||
|
|
clocks = <&ccu CLK_BUS_UART1>;
|
||
|
|
resets = <&ccu RST_BUS_UART1>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart2: serial@1c28800 {
|
||
|
|
compatible = "snps,dw-apb-uart";
|
||
|
|
reg = <0x01c28800 0x400>;
|
||
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg-shift = <2>;
|
||
|
|
reg-io-width = <4>;
|
||
|
|
clocks = <&ccu CLK_BUS_UART2>;
|
||
|
|
resets = <&ccu RST_BUS_UART2>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart3: serial@1c28c00 {
|
||
|
|
compatible = "snps,dw-apb-uart";
|
||
|
|
reg = <0x01c28c00 0x400>;
|
||
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg-shift = <2>;
|
||
|
|
reg-io-width = <4>;
|
||
|
|
clocks = <&ccu CLK_BUS_UART3>;
|
||
|
|
resets = <&ccu RST_BUS_UART3>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
uart4: serial@1c29000 {
|
||
|
|
compatible = "snps,dw-apb-uart";
|
||
|
|
reg = <0x01c29000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
reg-shift = <2>;
|
||
|
|
reg-io-width = <4>;
|
||
|
|
clocks = <&ccu CLK_BUS_UART4>;
|
||
|
|
resets = <&ccu RST_BUS_UART4>;
|
||
|
|
status = "disabled";
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c0: i2c@1c2ac00 {
|
||
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
||
|
|
reg = <0x01c2ac00 0x400>;
|
||
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&ccu CLK_BUS_I2C0>;
|
||
|
|
resets = <&ccu RST_BUS_I2C0>;
|
||
|
|
status = "disabled";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c1: i2c@1c2b000 {
|
||
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
||
|
|
reg = <0x01c2b000 0x400>;
|
||
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&ccu CLK_BUS_I2C1>;
|
||
|
|
resets = <&ccu RST_BUS_I2C1>;
|
||
|
|
status = "disabled";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
i2c2: i2c@1c2b400 {
|
||
|
|
compatible = "allwinner,sun6i-a31-i2c";
|
||
|
|
reg = <0x01c2b400 0x400>;
|
||
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&ccu CLK_BUS_I2C2>;
|
||
|
|
resets = <&ccu RST_BUS_I2C2>;
|
||
|
|
status = "disabled";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
|
||
|
|
spi0: spi@1c68000 {
|
||
|
|
compatible = "allwinner,sun8i-h3-spi";
|
||
|
|
reg = <0x01c68000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
|
||
|
|
clock-names = "ahb", "mod";
|
||
|
|
dmas = <&dma 23>, <&dma 23>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&spi0_pins>;
|
||
|
|
resets = <&ccu RST_BUS_SPI0>;
|
||
|
|
status = "disabled";
|
||
|
|
num-cs = <1>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
spi1: spi@1c69000 {
|
||
|
|
compatible = "allwinner,sun8i-h3-spi";
|
||
|
|
reg = <0x01c69000 0x1000>;
|
||
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
|
||
|
|
clock-names = "ahb", "mod";
|
||
|
|
dmas = <&dma 24>, <&dma 24>;
|
||
|
|
dma-names = "rx", "tx";
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&spi1_pins>;
|
||
|
|
resets = <&ccu RST_BUS_SPI1>;
|
||
|
|
status = "disabled";
|
||
|
|
num-cs = <1>;
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
|
||
|
|
emac: ethernet@1c30000 {
|
||
|
|
compatible = "allwinner,sun50i-a64-emac";
|
||
|
|
syscon = <&syscon>;
|
||
|
|
reg = <0x01c30000 0x10000>;
|
||
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
interrupt-names = "macirq";
|
||
|
|
resets = <&ccu RST_BUS_EMAC>;
|
||
|
|
reset-names = "stmmaceth";
|
||
|
|
clocks = <&ccu CLK_BUS_EMAC>;
|
||
|
|
clock-names = "stmmaceth";
|
||
|
|
status = "disabled";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
|
||
|
|
mdio: mdio {
|
||
|
|
compatible = "snps,dwmac-mdio";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
gic: interrupt-controller@1c81000 {
|
||
|
|
compatible = "arm,gic-400";
|
||
|
|
reg = <0x01c81000 0x1000>,
|
||
|
|
<0x01c82000 0x2000>,
|
||
|
|
<0x01c84000 0x2000>,
|
||
|
|
<0x01c86000 0x2000>;
|
||
|
|
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <3>;
|
||
|
|
};
|
||
|
|
|
||
|
|
rtc: rtc@1f00000 {
|
||
|
|
compatible = "allwinner,sun6i-a31-rtc";
|
||
|
|
reg = <0x01f00000 0x54>;
|
||
|
|
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
||
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
r_intc: interrupt-controller@1f00c00 {
|
||
|
|
compatible = "allwinner,sun50i-a64-r-intc",
|
||
|
|
"allwinner,sun6i-a31-r-intc";
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <2>;
|
||
|
|
reg = <0x01f00c00 0x400>;
|
||
|
|
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
};
|
||
|
|
|
||
|
|
r_ccu: clock@1f01400 {
|
||
|
|
compatible = "allwinner,sun50i-a64-r-ccu";
|
||
|
|
reg = <0x01f01400 0x100>;
|
||
|
|
clocks = <&osc24M>, <&osc32k>, <&iosc>,
|
||
|
|
<&ccu 11>;
|
||
|
|
clock-names = "hosc", "losc", "iosc", "pll-periph";
|
||
|
|
#clock-cells = <1>;
|
||
|
|
#reset-cells = <1>;
|
||
|
|
};
|
||
|
|
|
||
|
|
r_pio: pinctrl@1f02c00 {
|
||
|
|
compatible = "allwinner,sun50i-a64-r-pinctrl";
|
||
|
|
reg = <0x01f02c00 0x400>;
|
||
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, <&osc32k>;
|
||
|
|
clock-names = "apb", "hosc", "losc";
|
||
|
|
gpio-controller;
|
||
|
|
#gpio-cells = <3>;
|
||
|
|
interrupt-controller;
|
||
|
|
#interrupt-cells = <3>;
|
||
|
|
|
||
|
|
r_rsb_pins: rsb {
|
||
|
|
pins = "PL0", "PL1";
|
||
|
|
function = "s_rsb";
|
||
|
|
};
|
||
|
|
};
|
||
|
|
|
||
|
|
r_rsb: rsb@1f03400 {
|
||
|
|
compatible = "allwinner,sun8i-a23-rsb";
|
||
|
|
reg = <0x01f03400 0x400>;
|
||
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||
|
|
clocks = <&r_ccu 6>;
|
||
|
|
clock-frequency = <3000000>;
|
||
|
|
resets = <&r_ccu 2>;
|
||
|
|
pinctrl-names = "default";
|
||
|
|
pinctrl-0 = <&r_rsb_pins>;
|
||
|
|
status = "disabled";
|
||
|
|
#address-cells = <1>;
|
||
|
|
#size-cells = <0>;
|
||
|
|
};
|
||
|
|
};
|
||
|
|
};
|