83 lines
3.6 KiB
Plaintext
83 lines
3.6 KiB
Plaintext
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* Samsung I2S controller
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Required SoC Specific Properties:
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- compatible : should be one of the following.
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- samsung,s3c6410-i2s: for 8/16/24bit stereo I2S.
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- samsung,s5pv210-i2s: for 8/16/24bit multichannel(5.1) I2S with
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secondary fifo, s/w reset control and internal mux for root clk src.
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- samsung,exynos5420-i2s: for 8/16/24bit multichannel(5.1) I2S for
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playback, sterio channel capture, secondary fifo using internal
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or external dma, s/w reset control, internal mux for root clk src
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and 7.1 channel TDM support for playback. TDM (Time division multiplexing)
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is to allow transfer of multiple channel audio data on single data line.
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- samsung,exynos7-i2s: with all the available features of exynos5 i2s,
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exynos7 I2S has 7.1 channel TDM support for capture, secondary fifo
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with only external dma and more no.of root clk sampling frequencies.
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- samsung,exynos7-i2s1: I2S1 on previous samsung platforms supports
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stereo channels. exynos7 i2s1 upgraded to 5.1 multichannel with
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slightly modified bit offsets.
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- reg: physical base address of the controller and length of memory mapped
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region.
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- dmas: list of DMA controller phandle and DMA request line ordered pairs.
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- dma-names: identifier string for each DMA request line in the dmas property.
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These strings correspond 1:1 with the ordered pairs in dmas.
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- clocks: Handle to iis clock and RCLK source clk.
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- clock-names:
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i2s0 uses some base clks from CMU and some are from audio subsystem internal
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clock controller. The clock names for i2s0 should be "iis", "i2s_opclk0" and
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"i2s_opclk1" as shown in the example below.
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i2s1 and i2s2 uses clocks from CMU. The clock names for i2s1 and i2s2 should
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be "iis" and "i2s_opclk0".
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"iis" is the i2s bus clock and i2s_opclk0, i2s_opclk1 are sources of the root
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clk. i2s0 has internal mux to select the source of root clk and i2s1 and i2s2
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doesn't have any such mux.
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- #clock-cells: should be 1, this property must be present if the I2S device
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is a clock provider in terms of the common clock bindings, described in
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../clock/clock-bindings.txt.
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- clock-output-names: from the common clock bindings, names of the CDCLK
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I2S output clocks, suggested values are "i2s_cdclk0", "i2s_cdclk1",
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"i2s_cdclk3" for the I2S0, I2S1, I2S2 devices recpectively.
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There are following clocks available at the I2S device nodes:
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CLK_I2S_CDCLK - the CDCLK (CODECLKO) gate clock,
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CLK_I2S_RCLK_PSR - the RCLK prescaler divider clock (corresponding to the
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IISPSR register),
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CLK_I2S_RCLK_SRC - the RCLKSRC mux clock (corresponding to RCLKSRC bit in
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IISMOD register).
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Refer to the SoC datasheet for availability of the above clocks.
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The CLK_I2S_RCLK_PSR and CLK_I2S_RCLK_SRC clocks are usually only available
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in the IIS Multi Audio Interface (I2S0).
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Note: Old DTs may not have the #clock-cells, clock-output-names properties
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and then not use the I2S node as a clock supplier.
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Optional SoC Specific Properties:
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- samsung,idma-addr: Internal DMA register base address of the audio
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sub system(used in secondary sound source).
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- pinctrl-0: Should specify pin control groups used for this controller.
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- pinctrl-names: Should contain only one value - "default".
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Example:
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i2s0: i2s@3830000 {
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compatible = "samsung,s5pv210-i2s";
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reg = <0x03830000 0x100>;
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dmas = <&pdma0 10
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&pdma0 9
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&pdma0 8>;
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dma-names = "tx", "rx", "tx-sec";
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clocks = <&clock_audss EXYNOS_I2S_BUS>,
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<&clock_audss EXYNOS_I2S_BUS>,
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<&clock_audss EXYNOS_SCLK_I2S>;
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clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
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#clock-cells;
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clock-output-names = "i2s_cdclk0";
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samsung,idma-addr = <0x03000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_bus>;
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};
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