79 lines
2.9 KiB
Plaintext
79 lines
2.9 KiB
Plaintext
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Freescale Synchronous Audio Interface (SAI).
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The SAI is based on I2S module that used communicating with audio codecs,
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which provides a synchronous audio interface that supports fullduplex
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serial interfaces with frame synchronization such as I2S, AC97, TDM, and
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codec/DSP interfaces.
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Required properties:
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- compatible : Compatible list, contains "fsl,vf610-sai",
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"fsl,imx6sx-sai" or "fsl,imx6ul-sai"
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- reg : Offset and length of the register set for the device.
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- clocks : Must contain an entry for each entry in clock-names.
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- clock-names : Must include the "bus" for register access and
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"mclk1", "mclk2", "mclk3" for bit clock and frame
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clock providing.
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- dmas : Generic dma devicetree binding as described in
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Documentation/devicetree/bindings/dma/dma.txt.
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- dma-names : Two dmas have to be defined, "tx" and "rx".
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- pinctrl-names : Must contain a "default" entry.
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- pinctrl-NNN : One property must exist for each entry in
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pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
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for details of the property values.
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- big-endian : Boolean property, required if all the FTM_PWM
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registers are big-endian rather than little-endian.
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- lsb-first : Configures whether the LSB or the MSB is transmitted
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first for the fifo data. If this property is absent,
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the MSB is transmitted first as default, or the LSB
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is transmitted first.
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- fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
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that SAI will work in the synchronous mode (sync Tx
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with Rx) which means both the transimitter and the
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receiver will send and receive data by following
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receiver's bit clocks and frame sync clocks.
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- fsl,sai-asynchronous: This is a boolean property. If present, indicating
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that SAI will work in the asynchronous mode, which
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means both transimitter and receiver will send and
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receive data by following their own bit clocks and
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frame sync clocks separately.
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Optional properties (for mx6ul):
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- fsl,sai-mclk-direction-output: This is a boolean property. If present,
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indicates that SAI will output the SAI MCLK clock.
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Note:
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- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
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default synchronous mode (sync Rx with Tx) will be used, which means both
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transimitter and receiver will send and receive data by following clocks
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of transimitter.
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- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
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Example:
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sai2: sai@40031000 {
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compatible = "fsl,vf610-sai";
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reg = <0x40031000 0x1000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2_1>;
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clocks = <&clks VF610_CLK_PLATFORM_BUS>,
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<&clks VF610_CLK_SAI2>,
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<&clks 0>, <&clks 0>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dma-names = "tx", "rx";
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dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
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<&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
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big-endian;
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lsb-first;
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};
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