63 lines
1.9 KiB
Plaintext
63 lines
1.9 KiB
Plaintext
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Freescale Sony/Philips Digital Interface Format (S/PDIF) Controller
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The Freescale S/PDIF audio block is a stereo transceiver that allows the
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processor to receive and transmit digital audio via an coaxial cable or
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a fibre cable.
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Required properties:
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- compatible : Compatible list, must contain "fsl,imx35-spdif".
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- reg : Offset and length of the register set for the device.
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- interrupts : Contains the spdif interrupt.
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- dmas : Generic dma devicetree binding as described in
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Documentation/devicetree/bindings/dma/dma.txt.
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- dma-names : Two dmas have to be defined, "tx" and "rx".
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- clocks : Contains an entry for each entry in clock-names.
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- clock-names : Includes the following entries:
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"core" The core clock of spdif controller.
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"rxtx<0-7>" Clock source list for tx and rx clock.
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This clock list should be identical to the source
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list connecting to the spdif clock mux in "SPDIF
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Transceiver Clock Diagram" of SoC reference manual.
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It can also be referred to TxClk_Source bit of
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register SPDIF_STC.
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"spba" The spba clock is required when SPDIF is placed as a
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bus slave of the Shared Peripheral Bus and when two
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or more bus masters (CPU, DMA or DSP) try to access
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it. This property is optional depending on the SoC
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design.
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- big-endian : If this property is absent, the native endian mode
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will be in use as default, or the big endian mode
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will be in use for all the device registers.
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Example:
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spdif: spdif@2004000 {
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compatible = "fsl,imx35-spdif";
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reg = <0x02004000 0x4000>;
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interrupts = <0 52 0x04>;
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dmas = <&sdma 14 18 0>,
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<&sdma 15 18 0>;
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dma-names = "rx", "tx";
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clocks = <&clks 197>, <&clks 3>,
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<&clks 197>, <&clks 107>,
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<&clks 0>, <&clks 118>,
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<&clks 62>, <&clks 139>,
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<&clks 0>;
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clock-names = "core", "rxtx0",
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"rxtx1", "rxtx2",
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"rxtx3", "rxtx4",
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"rxtx5", "rxtx6",
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"rxtx7";
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big-endian;
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};
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